ICS85354AKT [ICSI]
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER; 双2 ： 1/1 ： 2差分 - 至LVPECL / ECL复用器
| 型号： | ICS85354AKT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER |
| 文件： | 总16页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS85354 is a 2:1/1:2 Multiplexer and a mem- • Dual 2:1/1:2 MUX
ICS
ber of the HiPerClockSTM family of high perfor-
• 3 LVPECL outputs
HiPerClockS™
mance clock solutions from ICS.The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one out-
put pin and the 1:2 MUX switches one input to one
• 3 differential clock inputs
• CLKx pair can accept the following differential input levels:
LVPECL, LVDS, CML
of two outputs.This device may be useful for multiplexing multi-
rate Ethernet Phys which have 100Mbit and 1000Mbit transmit/
receive pairs onto an optical SFP module which has a single
trasmit/receive pair. Please refer to the Application Block dia-
gram on page 2 of the data sheet.
• Maximum output frequency: 3GHz
• Part-to-part skew: 85ps (typical)
• Additive jitter, RMS: 0.03ps (typical)
• Propagation delay: 330ps (typical)
The ICS85354 is optimized for applications requiring very high
performance and has a maximum operating frequency in excess
of 2GHz.The device is packaged in a small, 3mm x 3mmVFQFN
package, making it ideal for use on space-constrained boards.
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SELA
16 15 14 13
CLKA0
nCLKA0
0
QB0
1
2
12 CLKA0
11 nCLKA0
10 CLKA1
QA
nQA
nQB0
CLKA1
nCLKA1
QB1
3
4
1
nQB1
9
nCLKA1
5
6
7
8
CLKB
nCLKB
QB0
nQB0
ICS85354
QB1
nQB1
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
CLK_SELB
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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1
PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
A TYPICAL APPLICATION FOR THE ICS85354
Used to connect a multi-rate PHY with the Tx/Rx pins of an
SFP Module.
Problem Addressed: How to mape the 2 Tx/Rx pairs of the
multi-rate PHY to the single Tx/Rx pair on the SFP Module.
MULTI-RATE PHY
SFP MODULE
Tx
➣
➣
100BaseFX
1000BaseX
Rx
➣
➣
Rx
Tx
➣
?
➣
Tx
Rx
MODE 1, 100BASEX CONNECTED TO SFP
All lines are differential pairs, but drawn as single-ended to
simplify the drawing.
Bold red lines
signal path.
are active connections highlighting the
CLK_SELA = 0
M
ULTI-RATE PHY
SFP MODULE
CLKA0
CLKA1
Tx
Rx
0
QA
Rx
1
100BaseFX
CLKB
Tx
QB0
QB1
CLK_SELB = 0
Tx
Rx
ICS85354
1000BaseX
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REV. B JUNE 8, 2004
2
PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-
TO-LVPECL/ECL MULTIPLEXER
MODE 2, 1000BASEX CONNECTED TO SFP
All lines are differential pairs, but drawn as single-ended to
simplify the drawing.
Bold red lines
the signal path.
are active connections highlighting
CLK_SELA = 1
M
ULTI-RATE PHY
SFP MODULE
CLKA0
CLKA1
Tx
Rx
0
QA
Rx
1
100BaseFX
CLKB
Tx
QB0
QB1
CLK_SELB = 1
Tx
Rx
ICS85354
1000BaseX
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PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Type
Output
Description
QB0, nQB0
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
3, 4
QB1, nQB1 Output
5
CLKB
Input
Input
Pulldown Non-inverting LVPECL/ECL differential clock input.
Pullup/
6
nCLKB
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
Clock select pin for QBx outputs. When HIGH, selects QB1, nQB1
Pulldown outputs. When LOW, selects QB0, nQB0 outputs.
LVCMOS/LVTTL interface levels.
7
CLK_SELB
Input
8
VEE
Power
Input
Input
Input
Negative supply pin.
Pullup/
9
nCLKA1
CLKA1
nCLKA0
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
10
11
Pulldown Non-inverting LVPECL differential clock input.
Pullup/
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
12
13
CLKA0
VCC
Input
Pulldown Non-inverting LVPECL differential clock input.
Positive supply pin.
Power
Clock select pin for QA outputs. When HIGH, selects QA output.
Pulldown
14
CLK_SELA
nQA, QA
Input
When LOW, selects nQA output. LVCMOS/LVTTL interface levels.
15, 16
Output
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN Input Pulldown Resistor
37.5
KΩ
Pullup/Pulldown Resistors
37.5
KΩ
RVCC/2
TABLE 3A. CONTROL INPUT FUNCTION TABLE, BANK A
Bank A
Control Inputs
Outputs
CLK_SELA
QA, nQA
0
1
Selects CLKA0, nCLKA0
Selects CLKA1, nCLKA1
TABLE 3B. CONTROL INPUT FUNCTION TABLE, BANK B
Bank B
Control Inputs
Outputs
CLK_SELB
QB0, nQB0
QB1, nQB1
Low
0
1
Follows CLKB input
Low
Follows CLKB input
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ICS85354
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D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V
Symbol Parameter
VCC Positive Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
3.465
2.625
V
V
2.375
2.5
38
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V
Symbol Parameter
Test Conditions
VCC = 2.5V or 3.3V
VCC = 2.5V or 3.3V
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage CLK_SELx
2
0
VCC + 0.3
0.8
V
V
Input Low Voltage
CLK_SELx
V
CC = VIN = 3.465V,
CC = VIN = 2.625V
CC = 3.465
2.625V, VIN = 0V
CLK_SELA,
CLK_SELB
IIH
IIL
Input High Current
150
µA
µA
V
V
CLK_SELA,
CLK_SELB
Input Low Current
-150
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ICS85354
Integrated
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D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V, VEE = 0V
-40°C
25°C
Typ
85°C
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Typ
Max
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Peak-to-Peak
Input Voltage
Input High Voltage
Common Mode Range;
NOTE 2, 3
VOH
VOL
VPP
VCC-1.125 VCC-1.025
VCC-1.895 VCC-1.755
VCC-0.92 VCC-1.075 VCC-1.005
VCC-0.93
VCC-1.005
VCC-0.97
VCC-0.935
V
V
VCC-1.62 VCC-1.875
VCC-1.78
800
VCC-1.685
1200
VCC-1.86
150
VCC-1.765
800
VCC-1.67
1200
150
1.2
800
1200
VCC
150
1.2
mV
VCMR
VCC
1.2
VCC
V
CLKAx,
Input
CLKB
IIH
150
150
150
µA
High Current nCLKAx,
nCLKB
CLKAx,
CLKB
nCLKAx,
nCLKB
-10
-10
-10
µA
µA
Input
Low Current
IIL
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VCC can vary +0.165V to -0.925V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB
is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VEE = -3.465V TO -2.375V, VCC = 0V
-40°C
Typ Max
25°C
Typ Max
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
150
Min
-1.075
-1.875
150
Min
-1.005
-1.86
150
-1.025
-1.755
800
-0.92
-1.62
1200
-1.005
-1.78
800
-0.93
-1.685
1200
-0.97
-1.765
800
-0.935
-1.67
1200
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
VEE+1.2V
VEE+1.2V
VEE+1.2V
V
VCMR
IIH
VCC
150
VCC
150
VCC
150
Input
CLKAx, CLKB
µA
High Current nCLKAx, nCLKB
-10
-10
-10
µA
µA
CLKAx, CLKB
Input
Low Current
IIL
-150
-150
-150
nCLKAx, nCLKB
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB
is VCC + 0.3V.
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ICS85354
Integrated
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D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V
Symbol Parameter Conditions Minimum Typical Maximum Units
fMAX
Output Frequency
3
GHz
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 3, 4
330
85
tsk(pp)
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.03
ps
MUX Isolation
55
dB
ps
tR/tF
Output Rise/Fall Time
20% to 80%
170
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85354
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D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLKA0, nCLKA1
nCLKB
LVPECL
VEE
VPP
VCMR
Cross Points
CLKA0, CLKA1
CLKB
nQx
VEE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLKA0,
nCLKA1
nCLKB
nQx
PART 1
Qx
CLKA0,
CLKA1
CLKB
nQA,
nQB0,
nQB1
nQy
PART 2
Qy
QA,
QB0,
QB1
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
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ICS85354
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D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER
T
ERMINATION
E
XAMPLE
F
IGURE 3B. 2.5V LVPECL DRIVER
T
ERMINATION
E
XAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
-
Zo = 50 Ohm
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS85354
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D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 4A to 4E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
R1
50
R2
50
LVHSTL
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85354.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85354 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 38mA = 131.7mW
Power (outputs)MAX = 27.83mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 27.83mW = 111.3mW
Total Power_MAX (3.465, with all outputs switching) = 131.7mW + 111.3mW = 243mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.243W * 51.5°C/W = 97.5°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
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UAL 2:1/1:2
DIFFERENTIAL
-
TO-LVPECL/ECL MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.005V
OH_MAX
CC_MAX
)
= 1.005
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.78V
OL_MAX
CC_MAX
)
= 1.78V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1.005V)/50Ω] * 1.005V = 20mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.78V)/50Ω] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
13
PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS85354 is: 210
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
14
PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
15
PRELIMINARY
ICS85354
Integrated
Circuit
Systems, Inc.
D
UAL 2:1/1:2
DIFFERENTIAL
-TO-LVPECL/ECL MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85354AK
Marking
Package
Count
120 per Tube
3500
Temperature
-40°C to 85°C
-40°C to 85°C
354A
354A
16 Lead VFQFN
16 Lead VFQFN on Tape and Reel
ICS85354AKT
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
16
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