ICS85401AKT [ICSI]
DIFFERENTIAL-TO-LVDS MULTIPLEXER; 差分至LVDS多路复用器
| 型号： | ICS85401AKT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-LVDS MULTIPLEXER |
| 文件： | 总11页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
GENERAL DESCRIPTION
FEATURES
The ICS85401 is a high performance 2:1 Differ- • 2:1 LVDS MUX
ICS
ential-to-LVDS Multiplexer and a member of the
• 1 LVDS output
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from ICS.The ICS85401 can also per-
form differential translation because the differ-
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85401 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
• 2 differential clock inputs can accept: LVPECL, LVDS, CML
• Maximum input/output frequency: >2.5GHz
• Translates LVCMOS/LVTTL input signals to LVDS levels by
using a resistor bias network on nCLK0, nCLK1
• Propagation delay: 460ps (maximum)
• Part-to-part skew: 100ps (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK0
nCLK0
0
16 15 14 13
CLK0
1
2
12 GND
11
10 nQ
GND
Q
nQ
nCLK0
Q
CLK1
nCLK1
1
CLK1
3
4
nCLK1
9
5
6
7
8
CLK_SEL
ICS85401
16-LeadVFQFN
3mm x 3mm x 0.95 package body
K Package
TopView
85401AK
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REV. A FEBRUARY 22, 2005
1
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
CLK0
Input
Input
Pulldown Non-inverting differential clock input.
Pullup/
Pulldown
2
nCLK0
CLK1
nCLK1
nc
Inverting differential clock input. VDD/2 default when left floating.
3
4
Input
Pulldown Non-inverting differential clock input.
Pullup/
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
5, 7, 16
Unused
Unused pins.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levels.
6
CLK_SEL
Input
8, 13
9, 12, 14, 15
10, 11
VDD
Power
Power
Output
Positive supply pins.
GND
nQ, Q
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
1
RPULLUP
37
37
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input
Clock Out
CLK
CLK_SEL
0
1
CLK0, nCLK0
CLK1, nCLK1
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REV. A FEBRUARY 22, 2005
2
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
51.5°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
40
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage CLK_SEL
2
VDD + 0.3
0.8
V
V
Input Low Voltage CLK_SEL
Input High Current CLK_SEL
Input Low Current CLK_SEL
-0.3
VDD = VIN = 3.465V
150
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
NOTE: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, "Output Load Test Circuit".
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CLK0, CLK1
VDD = VIN = 3.465V
150
150
µA
IIH
Input High Current
nCLK0, nCLK1
VDD = VIN = 3.465V
µA
µA
CLK0, CLK1
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
IIL
Input Low Current
nCLK0, nCLK1
V
-150
0.15
1.2
µA
V
VPP
Peak-to-Peak Input Voltage
0.8
1.2
VDD
VCMR
Common Mode Input Voltage; NOTE 1, 2
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
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REV. A FEBRUARY 22, 2005
3
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VOD
Differential Output Voltage
200
350
500
50
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.05
1.15
1.25
50
∆ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
>2.5
460
100
200
51
GHz
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
260
360
160
-55
tsk(pp)
tR / tF
odc
ps
20ꢀ to 80ꢀ
125
49
ps
ꢀ
MUX Isolation
dB
All parameters measured at ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A FEBRUARY 22, 2005
4
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V 5ꢀ
SCOPE
nCLK0,
nCLK1
Qx
Power Supply
Float GND
VPP
VCMR
Cross Points
LVDS
+
-
nCLK0,
nCLK1
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQ
PART 1
Q0x
Q
Pulse Width
tPERIOD
nQy
PART 2
Qy
tPW
odc =
tsk(pp)
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PART-TO-PART SKEW
nCLK0,
nCLK1
80ꢀ
80ꢀ
tR
CLK0,
CLK1
Clock
Outputs
20ꢀ
20ꢀ
nQ
tF
Q
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
VDD
VDD
out
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/∆ VOD
➤
VOS/∆ VOS
➤
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV. A FEBRUARY 22, 2005
5
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
A
PPLICATION NFORMATION
I
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω differ- put. For a multiple LVDS outputs buffer, if only partial outputs
ential transmission line environment, LVDS drivers require a are used, it is recommended to terminate the un-used outputs.
matched load termination of 100Ω across near the receiver in-
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100Ω DifferentialTransmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
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REV. A FEBRUARY 22, 2005
6
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
R1
50
R2
50
LVHSTL
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85401AK
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REV. A FEBRUARY 22, 2005
7
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
APPLICATION SCHEMATIC EXAMPLE
Figure 4 shows an example of ICS85401 application sche- decoupling capacitor should be located as close as possible
matic. This device can accept different types of input signal. to the power pin.
In this example, the input is driven by a LVDS driver. The
3.3V
C1
0.1u
3.3V
Zo = 50
R2
100
Zo = 50
1
2
3
4
12
11
10
9
Zo = 50
Zo = 50
CLK0
nCLK0
CLK1
GND
Q
nQ
+
-
LVDS
R1
nCLK1
GND
100
3.3V
U1
ICS85401
Zo = 50
3.3V
R3
100
R4
1K
C2
0.1u
Zo = 50
LVDS
F
IGURE 4. ICS85401 APPLICATION
SCHEMATIC
E
XAMPLE
RELIABILITY INFORMATION
T
ABLE 6. θJAVS. AIR
F
LOW
TABLE FOR 16 LEAD VFQFN
θJA byVelocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
T
RANSISTOR
C
OUNT
The transistor count for ICS85401 is: 132
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REV. A FEBRUARY 22, 2005
8
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
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REV. A FEBRUARY 22, 2005
9
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS85401AK
Marking
401A
Package
Shipping Packaging
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
16 Lead VFQFN
16 Lead VFQFN
ICS85401AKT
401A
2500 Tape & Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A FEBRUARY 22, 2005
10
ICS85401
2:1
TO-LVDS MULTIPLEXER
Integrated
Circuit
Systems, Inc.
D
IFFERENTIAL
-
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
T8
Page
8
Date
Add Schematic Layout.
8/23/04
11/17/04
2/22/05
A
10
1
Corrected count in Ordering Information Table
Pin Assignment - corrected label on pin 2.
A
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REV. A FEBRUARY 22, 2005
11
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