ICS8735AY-01T [ICSI]
1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR; 1 ： 5差分至3.3V LVPECL零延迟时钟发生器
| 型号： | ICS8735AY-01T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1:5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY CLOCK GENERATOR |
| 文件： | 总17页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8735-01 is a highly versatile 1:5 Differ- • 5 differential 3.3V LVPECL outputs
ICS
ential-to-3.3V LVPECL clock generator and a
• Selectable differential clock inputs
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8735-01 has a fully integrated PLL and can
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
be configured as zero delay buffer, multiplier or divider, and
has an output frequency range of 31.25MHz to 700MHz.The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The
external feedback allows the device to achieve “zero delay”
between the input clock and the output clocks.The PLL_SEL
pin can be used to bypass the PLL for system test and debug
purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: 50ps 100ps
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PLL_SEL
Q1
nQ1
÷1, ÷2, ÷4, ÷8,
0
÷16, ÷32, ÷64
CLK0
nCLK0
32 31 30 29 28 27 26 25
Q2
nQ2
0
SEL0
SEL1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCCO
Q3
1
CLK1
1
Q3
nQ3
nCLK1
CLK0
nQ3
Q2
PLL
Q4
nQ4
nCLK0
CLK1
CLK_SEL
ICS8735-01
nQ2
Q1
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
nCLK1
CLK_SEL
FB_IN
nFB_IN
nQ1
VCCO
MR
9
10 11 12 13 14 15 16
SEL0
SEL1
SEL2
SEL3
MR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
32-LeadVFQFN
5mm x 5mm x 0.95 package body
K Package
TopView
8735AY-01
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REV. F NOVEMBER 12, 2004
1
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
SEL0
Type
Description
1
2
3
4
5
6
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Input Pulldown Non-inverting differential clock input.
SEL1
CLK0
nCLK0
CLK1
nCLK1
Input
Pullup Inverting differential clock input.
Input Pulldown Non-inverting differential clock input.
Input
Pullup Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
7
CLK_SEL Input Pulldown
When LOW, selects CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the otuputs are enabled.
LVCMOS / LVTTL interface levels.
8
MR
Input Pulldown
Power
9, 32
10
VCC
nFB_IN
FB_IN
SEL2
VEE
Core supply pins.
Input
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
11
Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
12
13, 28
14, 15
Power
Negative supply pins.
nQ0, Q0 Output
VCCO Power
Differential output pair. LVPECL interface levels.
16, 17,
24, 25
Output supply pins.
18, 19
20, 21
22, 23
26, 27
29
nQ1, Q1 Output
nQ2, Q2 Output
nQ3, Q3 Output
nQ4, Q4 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
SEL3
VCCA
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
30
Power
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
31
PLL_SEL
Input
Pullup
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
8735AY-01
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REV. F NOVEMBER 12, 2004
2
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Outputs
Inputs
SEL0
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)*
250 - 700
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
x 2
x 2
x 4
x 4
x 8
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250 to 700MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0:Q4, nQ0:nQ4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 4
÷ 4
÷ 4
÷ 8
÷ 8
÷ 8
÷ 16
÷ 16
÷ 32
÷ 64
÷ 2
÷ 2
÷ 4
÷ 1
÷ 2
÷ 1
8735AY-01
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REV. F NOVEMBER 12, 2004
3
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
I
Outputs, VO
PackageThermal Impedance, θ
32 Lead LQFP
JA
47.9°C/W (0 lfpm)
34.8°C/W (0 lfpm)
32 LeadVFQFN
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
150
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
VIN = VCC = 3.465V
VIN = VCC = 3.465V
150
5
µA
µA
IIH
PLL_SEL
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
VIN = 0V, VCC = 3.465V
-5
µA
µA
IIL
Input Low Current
PLL_SEL
V
IN = 0V, VCC = 3.465V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
V
IN = VCC = 3.465V
150
5
µA
µA
µA
µA
V
Input
IIH
High Current
VIN = VCC = 3.465V
VIN = 0V, VCC = 3.465V
-5
-150
Input
IIL
Low Current
V
IN = 0V, VCC = 3.465V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
8735AY-01
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REV. F NOVEMBER 12, 2004
4
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO - 1.0
VCCO - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fIN Input Frequency
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum Typical Maximum Units
31.25
700
700
MHz
MHz
CLK0, nCLK0,
CLK1, nCLK1
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
700
4.2
150
25
MHz
ns
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
PLL_SEL = 0V, f ≤ 700MHz
3.4
-50
t(Ø)
tsk(o)
tjit(cc)
tjit(θ)
tL
PLL_SEL = 3.3V
50
ps
ps
25
ps
50
ps
1
ms
ps
tR
Output Rise Time
20ꢀ to 80ꢀ @ 50MHz
20ꢀ to 80ꢀ @ 50MHz
300
300
47
700
700
53
tF
Output Fall Time
ps
odc
Output Duty Cycle
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
8735AY-01
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REV. F NOVEMBER 12, 2004
5
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
VCCA
,
Qx
,
VCCO
nCLK0,
nCLK1
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
CLK0,
CLK1
-1.3V 0.165V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nQ0:nQ4
Q0:Q4
➤
➤
➤
tcycle n
tcycle n+1
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQ0:nQ4
80ꢀ
tF
80ꢀ
Q0:Q4
VSWING
20ꢀ
Pulse Width
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nCLK0,
nCLK1
CLK0,
CLK1
VOH
VOL
nCLK0,
nCLK1
CLK0,
CLK1
nFB_IN
VOH
VOL
FB_IN
nQ0:nQ4
➤
t(Ø)
➤
Q0:Q4
tPD
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PROPAGATION DELAY
PHASE JITTER & STATIC PHASE OFFSET
8735AY-01
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REV. F NOVEMBER 12, 2004
6
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8735AY-01
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REV. F NOVEMBER 12, 2004
7
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
8735AY-01
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REV. F NOVEMBER 12, 2004
8
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8735-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 4 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
10Ω
.01µF
VCCA
10µF
.01µF
FIGURE 4. POWER SUPPLY FILTERING
LAYOUT GUIDELINE
The schematic of the ICS8735-01 layout example is shown in depend on the selected component types, the density of the
Figure 5A. The ICS8735-01 recommended PCB board layout components, the density of the traces, and the stack up of the
for this example is shown in Figure 5B. This layout example is P.C.board.
used as a general guideline.The layout in the actual system will
VCC
SP = Space (i.e. not intstalled)
R7
VCC
VCCA
RU2
SP
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
SEL[3:0] = 0101,
Divide by 2
10
C11
0.01u
CLK_SEL
PLL_SEL
SEL0
C16
10u
SEL1
SEL2
SEL3
Zo = 50 Ohm
Zo = 50 Ohm
(77.76 MHz)
+
-
RD2
1K
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
VCC
VCCO
LVPECL_input
R5
50
R4
50
U1
3.3V
(155.52 MHz)
Zo = 50 Ohm
Output
Termination
Example
SEL0
SEL1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
VCCO
R6
50
Q3
nQ3
Q2
nQ2
Q1
nQ1
VCCO
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
Zo = 50 Ohm
CLK_SEL
3.3V PECL Driver
Bypass capacitor located near the power pins
R8
50
R9
50
(U1-9)
(U1-32)
VCC
8735-01
VCC=3.3V
C1
0.1uF
C6
0.1uF
VCCO=3.3V
R10
50
SEL2
(U1-16)
(U1-17)
(U1-24)
(U1-25)
VCCO
R2
50
R1
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
R3
50
FIGURE 5A. ICS8735-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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8735AY-01
REV. F NOVEMBER 12, 2004
9
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
The following component footprints are used in this layout
example:
of the trace and the trace delay might be restricted by the
available space on the board and the component location.
While routing the traces, the clock signal traces should be routed
first and should be locked prior to routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors C1, C6, C2, C4, C5, and C7,
as close as possible to the power pins. If space allows, place-
ment of the decoupling capacitor on the component side is
preferred. This can reduce unwanted inductance between the
decoupling capacitor and the power pin caused by the via.
length.
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital sys-
tems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge
or excessive ring back can cause system failure. The shape
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
R7
C16
C11
C7
VCCO
C6
C5
VCC
U1
Pin 1
VCCA
VIA
50 Ohm
Traces
C4
C1
C2
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8735-01
8735AY-01
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REV. F NOVEMBER 12, 2004
10
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8735-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8735-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 520mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 520mW + 151mW = 671mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 7A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.671W * 42.1°C/W = 98°C. This is well below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7A. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC StandardTest Boards
34.8C/W
8735AY-01
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REV. F NOVEMBER 12, 2004
11
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
12
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 8A. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP PACKAGE
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 8B. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
θJA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC StandardTest Boards
34.8C/W
TRANSISTOR COUNT
The transistor count for ICS8735-01 is: 2969
8735AY-01
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REV. F NOVEMBER 12, 2004
13
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
8735AY-01
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REV. F NOVEMBER 12, 2004
14
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
8
8
5.0
D2
E
1.25
3.25
5.0
E2
L
1.25
0.30
3.25
0.50
Reference Document: JEDEC Publication 95, MO-220
8735AY-01
www.icst.com/products/hiperclocks.html
REV. F NOVEMBER 12, 2004
15
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8735AY-01
ICS8735AY-01T
ICS8735AK-01
ICS8735AK-01T
ICS8735AY-01
ICS8735AY-01
ICS8735AK-01
ICS8735AK-01
32 Lead LQFP
32 Lead LQFP on Tape and Reel
32 Lead VFQFN
490 per Tray
2500
32 Lead VFQFN on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8735AY-01
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REV. F NOVEMBER 12, 2004
16
ICS8735-01
Integrated
Circuit
Systems, Inc.
1:5 DIFFERENTIAL
-
TO-3.3V LVPECL
ZERO
D
ELAY
CLOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
tPD row changed the Test Condtions from 0MHz < f ≤ 700MHz to f ≤ 700MHz.
t(Ø) row changed Parameter name from PLL Reference Zero Delay to
Static Phase Offset.
B
T5
5
10/12/01
tjit(θ) row changed 85 Max. to 50 Max.
C
C
T4A
4
1
Added ICCA row.
10/30/01
11/1/01
Updated Block Diagram.
T3A
T6
3
5
Added note at end of the table.
Added Note 6.
C
11/19/01
C
C
Figure 11
10
Revised Figure 11, LVPECL Zero Delay Buffer Schematic Example
12/3/01
6/3/02
10
2
Added Termination for LVPECL Outputs section
Pin Description Table - revised MR description.
T2
6
3.3V Output Load Test Circuit Diagram, revised VEE equation from
"-1.3V 0.135V" to " -1.3V 0.165V".
C
D
E
8/19/02
9/17/02
12/3/02
8
5
Revised Output Rise/Fall Time Diagram.
T4D
T6
LVPECL table - corrected VSWING from 0.9 max. to 1.0 max.
AC Table - changed tPD from 3.6 min. to 3.4 min, deleted 3.9 typical.
Updated VCC pin description to read Core supply pins from Positive supply pins.
5
T1
2
4
T4A
Updated VCC to read Core Supply Voltage from Positive Supply Voltage.
IEE, deleted 100mA typical and added 150mA Maximum.
Updated format.
T1
T2
2
8
Pin Description Table - updated MR description.
E
F
1/31/03
Corrected LVPECL Zero Delay Buffer Schematic Example.
Add 32 Lead VFQFN package throughout data sheet.
2
8
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added Differential Clock Input Interface Application Section.
11/12/04
8735AY-01
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REV. F NOVEMBER 12, 2004
17
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