ICS874005AGLFT [ICSI]
PCI EXPRESS TM JITTER ATTENUATOR; PCI EXPRESS TM抖动衰减器型号: | ICS874005AGLFT |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | PCI EXPRESS TM JITTER ATTENUATOR |
文件: | 总12页 (文件大小:188K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS874005 is a high performance Diff- • Five differential LVDS output pairs
ICS
HiPerClockS™
erential-to-LVDS Jitter Attenuator designed for
• One differential clock input
use in PCI Express systems. In some PCI
Express systems, such as those found in
desktop PCs, the PCI Express clocks are
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874005 has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated.The 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have
x20 multipliers while others have than x25 multipliers, the
874005 can be set for 1:1 mode or 5/4 multiplication mode
(i.e. 100MHz input/125MHz output) using the F_SEL pins.
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V operating supply
• 3 bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PLL BANDWIDTH
The ICS874005 uses ICS 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package,
making it ideal for use in space constrained applications
such as PCI Express add-in cards.
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
PIN ASSIGNMENT
BLOCK DIAGRAM
Pulldown
OEA
nQB2
nQA1
QA1
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
QB2
VDDO
QB1
Pulldown
F_SELA
BW_SEL
QA0
Float
F_SELA
0 = ~200kHz
Float = ~400kHz
VDDO
nQB1
0
1
÷5 (default)
÷4
nQA0
QA1
5
6
7
8
QA0
nQA0
MR
BW_SEL
VDDA
QB0
1 = ~800kHz
nQB0
F_SELB
OEB
Pulldown
Pullup
CLK
Phase
Detector
VCO
nQA1
QB0
9
490 - 640MHz
nCLK
GND
GND
nCLK
10
11
12
F_SELA
VDD
F_SELB
0
1
÷5 (default)
÷4
OEA
CLK
nQB0
QB1
M = ÷5 (fixed)
ICS874005
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
nQB1
QB2
G Package
nQB2
Top View
Pulldown
F_SELB
MR
Pulldown
Pullup
OEB
874005AG
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REV.A JANUARY 25, 2006
1
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 24
2, 3
Name
nQB2, QB2
nQA1, QA1
VDDO
Type
Description
Output
Output
Power
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pins.
4, 23
5, 6
QA0, nQA0
nFB_OUT
Differential output pair. LVDS interface levels.
Inverting differential feedback output.
6
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
7
MR
Input
Pulldown
Pullup/
Pulldown
8
BW_SEL
VDDA
Input
Power
Input
PLL Bandwidth input. See Table 3B.
9
Analog supply pin.
Frequency select pin for QAx/nQAx outputs.
LVCMOS/LVTTL interface levels.
10
11
F_SELA
VDD
Pulldown
Pullup
Power
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
12
OEA
Input
13
14
CLK
nCLK
GND
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Power supply ground.
15, 16
Power
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
17
OEB
Input
Pullup
Frequency select pin for QBx/nQBx outputs.
LVCMOS/LVTTL interface levels.
18
F_SELB
Input
Pulldown
19, 20
21, 22
nQB0, QB0
nQB1, QB1
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs
PLL
Inputs
Outputs
Bandwidth
~200kHz
~800kHz
~400kHz
PLL_BW
OEA/OEB QAx/nQAx QBx/nQBx
0
1
0
1
HiZ
HiZ
Enabled
Enabled
Float
874005AG
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REV.A JANUARY 25, 2006
2
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
85
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
115
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
OEA, OEB, MR,
F_SELA, F_SELB
2
VDD + 0.3
V
V
V
VIH
Input High Voltage
BW_SEL
V
DD - 0.4
-0.3
OEA, OEB, MR,
F_SELA, F_SELB
0.8
VIL
VIM
IIH
Input Low Voltage
Input Mid Voltage
Input High Current
BW_SEL
BW_SEL
OEA, OEB
F_SELA, F_SELB
MR, BW_SEL
BW_SEL,
OEA, OEB
MR,
F_SELA, F_SELB
0.4
VDD/2 + 0.1
5
V
V
VDD/2 - 0.1
VDD = VIN = 3.465V
µA
V
DD = VIN = 3.465V
DD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
150
µA
µA
µA
V
-150
-5
IIL
Input Low Current
874005AG
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REV.A JANUARY 25, 2006
3
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
µA
nCLK
CLK
5
150
µA
IIL
Input Low Current
nCLK
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
275
375
485
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.2
1.35
1.5
50
Δ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
98
160
30
MHz
ps
tjit(cc)
tsk(o)
tR / tF
odc
Cycle-to-Cycle Jitter, NOTE 1
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
15
90
ps
20ꢀ to 80ꢀ
300
48
550
52
ps
ꢀ
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
874005AG
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REV.A JANUARY 25, 2006
4
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD,
VDDO
VDDA
VDD
nCLK
CLK
SCOPE
Qx
3.3V 5ꢀ
POWER SUPPLY
Float GND
VPP
VCMR
Cross Points
LVDS
+
–
nQx
GND
3.3V LVDS OUTPUT LOAD ACTEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0, nQA1
nQB0:nQB2
nQx
Qx
QA0, QA1
QB0:QB2
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nQA0, nQA1
nQB0:nQB2
80ꢀ
tF
80ꢀ
QA0, QA1
QB0:QB2
VSWING
20ꢀ
tPW
Clock
Outputs
20ꢀ
tPERIOD
tR
tPW
tPERIOD
odc =
x 100ꢀ
OUTPUT RISE/FALLTIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSETVOLTAGE SETUP
874005AG
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REV.A JANUARY 25, 2006
5
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS874005 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V,V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
874005AG
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REV.A JANUARY 25, 2006
6
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
LVDS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
874005AG
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REV.A JANUARY 25, 2006
7
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
3.3V
3.3V
LVDS_Driver
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVERT ERMINATION
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS874005 application sche- decoupling capacitor should be located as close as possible
matic. In this example, the device is operated at VDD=3.3V.The to the power pin. The input is driven by a 3.3V LVPECL driver.
VDD = 3.3V
VDDO = 3.3V
Zo = 50 Ohm
+
-
U1
R2
100
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
Zo = 50 Ohm
nQB2
nQA1
QA1
VDDO
QA0
nQAO
MR
BW_SEL
VDDA
F_SELA
VDD
QB2
VDDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
R1
10
C3
10uF
C4
0.01u
F_SELB
OEB
MR
BW_SEL
10
11
12
F_SELA
OEA
Zo = 50 Ohm
OEA
+
-
874005_tssop24
R3
100
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
nCLK
CLK
LVPECL Driver
R4
50
R5
50
(U1:11)
(U1:4) (U1:23)
R6
50
C5
10uf
C6
.1uf
C7
.1uf
C8
.1uf
FIGURE 5. ICS874005 SCHEMATIC EXAMPLE
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874005AG
REV.A JANUARY 25, 2006
8
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874005.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS874005 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (85mA + 15mA) = 346.5mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 115mA = 398.48mW
Total Power_MAX = 346.5mW + 398.48mW = 745mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per
Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.745W * 63°C/W = 117°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-LEADTSSOP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
874005AG
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REV.A JANUARY 25, 2006
9
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 24 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
TRANSISTOR COUNT
The transistor count for ICS874005 is: 1206
874005AG
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REV.A JANUARY 25, 2006
10
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
874005AG
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REV.A JANUARY 25, 2006
11
ICS874005
PCI EXPRESS™
JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
TABLE 9.ORDERING INFORMATION
Part/Order Number
ICS874005AG
Marking
ICS874005AG
ICS874005AG
TBD
Package
Shipping Packaging
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
24 Lead TSSOP
tube
ICS874005AGT
ICS874005AGLF
ICS874005AGLFT
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademarks, HiPerClockS and FemtoClock are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
874005AG
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REV.A JANUARY 25, 2006
12
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IDT
ICS8741004AGILF
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
IDT
ICS8741004AGIT
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
ICS8741004AGT
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4 40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
IDT
ICS8741004BGILF
PLL Based Clock Driver, 8741004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, TSSOP-24
IDT
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