ICS9148BF-04 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9148BF-04 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总14页 (文件大小：624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148B-04
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
Features
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz
The ICS9148B-04 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
2.5Vor3.3Voutputs:CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center
2.6 ns.
No external load cap for CL=18pF crystals
±250 ps CPU, PCI clock skew
Features include four CPU, seven PCI and Twelve SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Plus the IOAPIC output powered byVDDL1.
One 48 MHz for USB, and one 24 MHz clock for Super IO.
Spread Spectrum built in - ±1.5% modulation to reduce the
EMI. Serial programming I2C interface allows changing
functions, stop clock programing and Frequency selection.
Rise time adjustment for VDD at 3.3V or 2.5V CPU.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be
stable within 2ms after power-up. It is not recommended to
use I/O dual function pin for the slots (ISA, PCI, CPU, DIMM).
The add on card might have a pull up or pull down.
400ps (cycle to cycle) CPU jitter
Smooth frequency switch, with selections from 50 to 83.3
MHzCPU.
I2C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48pin300milSSOPpackage
3.3V operation, 5V tolerant input.
Pin Configuration
Block Diagram
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-04 RevB01/20/98
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148B-04
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
REF0
PWR Ref (0:1), XTAL power supply, nominal 3.3V
OUT 14.318 MHz reference clock.
2
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU,
CPU3.3#_2.51,2
IN
LOW=3.3V CPU1. Latched input2
3,9,16,22,27,
33,39,45
GND
X1
PWR Ground
Crystal input, has internal load cap (33pF) and feedback
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
5
X2
OUT
6,14
VDD2
PCICLK_F
FS11, 2
PWR Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
OUT Free running PCI clock
Frequency select pin. Latched Input
IN
7
PCICLK0
FS21, 2
OUT PCI clock output.
8
IN
Frequency select pin. Latched Input
10, 11, 12, 13
PCICLK(1:4)
PCICLK5
OUT PCI clock outputs.
OUT PCI clock output. (In desktop mode, MODE=1)
15
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
PCI_STOP#1
IN
17, 18, 20, 21,
28, 29, 31, 32, SDRAM (0:11)
34, 35,37,38
OUT SDRAM clock outputs.
Supply for SDRAM (0:11), PLL Core and 24, 48MHz clocks,
nominal 3.3V.
19,30,36
VDD3
PWR
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
24MHz output clock
24MHz
OUT
25
Pin 15, pin 46 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
MODE1, 2
IN
48MHz
FS01, 2
OUT 48MHz output clock
26
Frequency select pin. Latched Input
IN
40, 41, 43, 44
42
CPUCLK(0:3)
VDDL2
OUT CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
PWR Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318 MHz reference clock, (in Desktop Mode, MODE=1) This
REF output is the STRONGER buffer for ISA BUS loads.
REF1
OUT
46
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in
Mobile Mode, MODE=0)
CPU_STOP#1
IN
47
48
IOAPIC
VDDL1
OUT IOAPIC clock output. 14.318 MHz Powered by VDDL1.
PWR Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi toVDD or GND for logic low.
2
ICS9148B-04
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 46
Pin 15
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
REF1
(OUTPUT)
PCICLK5
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
and SDRAM
CPUCLK
Outputs
PCICLK
(0:5)
Crystal
OSC
CPU_STOP# PCI_STOP#
VCO
0
1
1
1
1
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Functionality
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
CPU,
SDRAM(MHz)
50.0
PCICLK
(MHz)
25.0 (1/2 CPU)
32
41.65 (1/2 CPU)
34.25 (1/2 CPU)
33.3
37.5 (1/2 CPU)
30.0 (1/2 CPU)
33.4 (1/2 CPU)
REF, IOAPIC
(MHz)
FS2
FS1
FS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
75.0
83.3
68.5
83.3
75.0
60.0
66.8
3
ICS9148B-04
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
+ 8 bits dummy
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
+ 8 bits dummy
Byte count
ACK
ACK
A(6:0) & R/W#
D2(H)
command code
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4protocol.
Clock Generator
Address (7 bits)
Byte 0
ACK
Byte 1
ACK
ACK
Byte 0, 1, 2, etc in sequence until STOP.
A(6:0) & R/W#
D3(H)
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H.
At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit 7
0
Bit6 Bit5 Bit4 CPU clock
PCI
111
110
101
100
011
010
001
000
66.8
60.0
75.0
83.3
68.5
83.3
75.0
50.0
33.4(1/2 CPU)
30.0 (1/2 CPU)
37.5 (1/2 CPU)
33.3
34.5 (1/2 CPU)
41.65 (1/2 CPU)
32.0
Note 1. Default at Power-up will be for latched logic
inputs to define frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1 to use Bits
6:4, then these should be defined to desired
frequency at same write cycle.
Bit 6:4
Note 1
25.0 (1/2 CPU)
Note: PWD = Power-Up Default
0 - Frequency is selected by hardware select,
Latched Inputs
Bit 3
0
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Bit 2
Bit 1
Bit 0
0
0
0
I2C is a trademark of Philips Corporation
1- Tristate all outputs
4
ICS9148B-04
Byte 1: CPU,Active/InactiveRegister
(1 = enable, 0 = disable)
Byte 2: PCIActive/Inactive Register(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Pin # PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
(Desktop only)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Bit
Pin #
PWD
Description
(Reserved)
-
7
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
(Reserved)
Bit 5
15
1
-
(Reserved)
-
(Reserved)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
14
12
11
10
8
1
1
1
1
1
40
41
43
44
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
2. PCICLK5 only in Desktop Mode
Byte3:SDRAMActive/InactiveRegister
(1 = enable, 0 = disable)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
-
17
18
20
21
PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching. These outputs are designed to be
configured at power-on and are not expected to be
configured during the normal modes of operation.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Byte 6: Optional Register For Possible Future Requirements
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
IOAPIC (Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit
Pin #
PWD
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled from
switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the
normal modes of operation.
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Note: PWD = Power-Up Default
2. REF1 only in Desktop Mode
5
ICS9148B-04
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148B-04. The minimum that the CPU clock is enabled (CPU_STOP# high pulse)
is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the CPU clocks inside the ICS9148B-04.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
6
ICS9148B-04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148B-04. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9148B-04 internally. The minimum that the PCICLK (0:5) clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off
latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
7
ICS9148B-04
Shared Pin Operation -
Input/Output Pins
header may be used.
Pins 2, 7, 8, 25, and 26 on the ICS9148B-04 serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 4-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic
1) power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
Fig. 1
8
ICS9148B-04
Fig. 2a
Fig. 2b
9
ICS9148B-04
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
V
IH
2
V +0.3
V
V
DD
V
IL
V -0.3
SS
0.8
5
IIH
IIL1
IIL2
V = V
0.1
2
µA
µA
µA
mA
IN
DD
V =0V; Inputs with no pull-up resistors
-5
IN
V = 0 V; Inputs with pull-up resistors
-200
-100
100
IN
IDD3.3OP CL = 0 pF; Select @ 66MHz
160
Supply Current
Input Frequency
Input Capacitance1
F
V
DD = 3.3 V
12
27
14.318
36
16
MHz
i
C
IN
Logic Inputs
X1 & X2 pins
5
pF
pF
C
INX
45
Transition Time1
ClkStabilization1
Skew1
Ttrans
To 1st crossing of target Freq.
2
2
ms
ms
TSTAB
FromVDD = 3.3 Vto 1% target Freq.
tCPU-SDRAM1
V = 1.5 V
T
500
4
ps
ns
tCPU-PCI1 V = 1.5 V
T
1
2.6
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5V+/-5% (unless otherwise stated)
PARAMETER
SYMBOL
IDD2.5OP
CONDITIONS
MIN
TYP MAX UNITS
Operating Supply Current
CL = 0pF; Select @ 66.8MHz
8
20
mA
Skew1
tCPU-SDRAM2 V = 1.5 V; V = 1.25 V
800
4
ps
ps
T
TL
tCPU-PCI2
V = 1.5 V; V = 1.25 V
T TL
1
1Guaranteed by design, not 100% tested in production.
10
ICS9148B-04
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V+/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
Output Impedance1
SYMBOL
RDSP2B
CONDITIONS
MIN
13.5
TYP
MAX UNITS
VO = VDD*(0.5)
45
45
Ohm
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2B
VOH2B
VOL2B
IOH2B
VO = VDD*(0.5)
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
13.5
2
Ohm
V
2.2
0.3
-20
26
0.4
-16
V
mA
mA
IOL2B
19
45
Rise Time1
Fall Time1
Duty Cycle1
tr2B
tf2 B
dt2B
tsk2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
2.2
1.1
2.5
1.6
55
ns
ns
%
ps
ps
ps
ps
Skew1
VT = 1.25 V
250
400
150
300
Jitter, Cycle-to-cycle1
Jitter, One Sigma1
Jitter, Absolute1
tjcyc-cyc2B VT = 1.25 V
200
50
tj1s2B
VT = 1.25 V
VT = 1.25 V
tjabs2B
-300
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output Impedance1
SYMBOL
RDSP1
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
24
24
Ohm
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
VO = VDD*(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ohm
V
2.4
3
0.2
-60
50
0.4
-40
V
mA
mA
IOL1
41
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.2
51
2
2
ns
ns
%
ps
dt1
tsk1
55
250
VT = 1.5 V
100
Jitter, One Sigma1
tj1s1
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
100
200
300
400
ps
ps
tj1s1a
Jitter, Absolute1
tjabs1
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-500
500
ps
ps
tjabs1a
-1000
1000
1Guaranteed by design, not 100% tested in production.
11
ICS9148B-04
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output Impedance1
SYMBOL
RDSP1
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
24
24
Ω
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
VO = VDD*(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
V
2.4
3
0.2
-60
50
0.4
-40
V
mA
mA
IOL1
41
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Tr1
Tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.2
52
2
2
ns
ns
%
ps
ps
ps
Dt1
55
Tsk1
Tj1s1
Tjabs1
VT = 1.5 V
150
50
250
150
+250
Jitter, One Sigma1
Jitter, Absolute1
VT = 1.5 V
VT = 1.5 V
-250
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5%; CL = 20 pF
PARAMETER
Output Impedance1
SYMBOL
RDSP4B
CONDITIONS
MIN
13.5
TYP MAX UNITS
VO = VDD*(0.5)
45
45
Ohm
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN4B
VOH4B
VOL4B
IOH4B
VO = VDD*(0.5)
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
13.5
2
Ohm
V
2.2
0.3
-20
26
0.4
-16
V
mA
mA
IOL4B
19
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4 B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.3
1.7
1.6
60
3
ns
ns
%
%
%
Dt4B
50
-5
Jitter, One Sigma1
Jitter, Absolute1
Tj1s4B
Tjabs4B
VT = 1.25 V
1
VT = 1.25 V
5
1Guaranteed by design, not 100% tested in production.
12
ICS9148B-04
Electrical Characteristics - 24,48MHz, REF(0:1)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
SYMBOL
RDSP5
CONDITIONS
MIN
20
TYP MAX UNITS
VO = VDD*(0.5)
60
60
Ohm
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VOH5
VOL5
IOH5
VO = VDD*(0.5)
IOH = -16 mA
IOL = 9 mA
20
Ohm
V
2.4
2.6
0.3
-32
25
0.4
-22
V
VOH = 2.0 V
VOL = 0.8 V
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.7
1.6
53
1
4
4
ns
ns
%
%
%
dt5
55
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
8
1Guaranteed by design, not 100% tested in production.
13
ICS9148B-04
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
A
A1
A2
B
AC
.625
.630
48
C
D
See Variations
E
.292
.296
.299
e
H
h
L
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9148BF-04
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
14
相关型号：
ICS9148BF-04LF
Processor Specific Clock Generator, 83.3MHz, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48
SPECTRUM
©2020 ICPDF网 联系我们和版权申明