ICS9148F-11 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUMTM; 频率发生器和集成缓冲器对PENTIUMTM
| 型号： | ICS9148F-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUMTM |
| 文件： | 总14页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-11
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
Features
Generates four processor, six bus, one 14.31818MHz and 12
TheICS9148-11generatesallclocksrequiredforhighspeedRISC
or CISC microprocessor systems such as Intel PentiumPro. An
output enable pin is provided for testability. MODE allows power
management functions: CPU_STOP#, PCI_STOP# &
PWR_DWN#.
SDRAMclocks.
Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on BUS clocks.
CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
Test clock mode eases system design
Customconfigurationsavailable
VDD(1:3) - 3.3V ±10%
(inputs5Vtolerantw/seriesR)
HighdriveBCLKoutputstypicallyprovidegreaterthan1V/nsslew
rateinto30pFloads.PCLKoutputstypicallyprovidebetterthan1V/
nsslewrateinto20pFloadswhilemaintaining
The REF clock outputs typically provide better than 0.5V/ns slew
rates.
50±
5% duty cycle.
VDDL(1:2) - 2.5V or 3.3V ±5%
PCserialconfigurationinterface
PowerManagementControlInputpins
48-pin SSOP package
Block Diagram
Pin Configuration
48-Pin SSOP
Functionality
CPUCLK,
SDRAM
(MHz)
X1, REF
(MHz)
PCICLK
(MHz)
OE
0
1
High-Z
66.6
High-Z
14.318
High-Z
33.3
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-11 RevB12/09/97P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-11
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
2
REF0
GND
OUT 14.318 MHz reference clock outputs.
PWR Ground.
3, 9, 16, 22, 27,
33, 39, 45
XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed
back resistor from X2
4
X1
IN
XTAL_OUT Crystal output, has internal load cap 33pF
5
25
7
X2
MODE
PCLK_F
OUT
IN
Mode select pin for enabling power management features.
OUT Free running BUS clock during PCI_STOP# = 0.
8, 10, 11, 12
13, 15
PCICLK (0:5)
OUT BUS clock outputs.
26
23
24
OE
SDATA
SCLK
IN
IN
IN
Logic input for output enable, tristates all outputs when low.
Serial data in for serial config port.
Clock input for serial config port.
1, 6, 14,
19, 30, 36,
17, 18, 20, 21,
32, 34, 35, 37, 38 (0:4) (8:11)
VDD1, VDD2,
VDD3
SDRAM
PWR Nominal 3.3V power supply, see power groups for function.
OUT SDRAM clocks 66.6MHz.
CPU and IOAPIC clock power supply, either
2.5 or 3.3V nominal
42, 48
VDDL2, VDDL1
PWR
40, 41, 43, 44
46, 47
CPUCLK (0:3)
IOAPIC (0:1)
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
SDRAM5
PWR_DWN#
OUT CPU output clocks, powered by VDDL2 (66.6 MHz)
OUT IOAPIC clock output, (14.318 MHz) powered by VDDL1
OUT SDRAM clock 66.6 MHz selected
28
29
31
IN
OUT SDRAM clock 66.6 MHz selected
IN Halts CPUCLK clocks at logic "0" level when low
OUT SDRAM clock 66.6 MHz selected
IN Powers down chip, active low
Halts PCICLK (0:5) at logic "0" level when low
Power Groups
VDD1 = REF0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#,
SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core.
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
2
ICS9148-11
Power-On Conditions
MODE
PIN #
44, 43, 41, 40
DESCRIPTION
CPUCLKs
FUNCTION
66.6 MHz - w/serial config enable/disable
38, 37, 35, 34,
32, 31, 21, 20,
18, 17, 29, 28
SDRAM
66.6 MHz - All SDRAM outputs
1
8, 10, 11,
12, 14, 15, 7
PCICLKs
PCI_STOP#
CPU_STOP#
33.3 MHz - w/serial config enable/disable
Power Management, PCI (0:5) Clocks Stopped
when low
Power Management, CPU (0:3) Clocks Stopped
when low
28
29
SDRAM/PWR
_DWN#
31
Used as PWR_DWN# when low
33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management
66.6 MHz - CPU Clocks w/external Stop Control and
serial config individual enable/disable.
7
PCICLK_F
CPUCLKs
0
44, 43, 41, 40
38, 37, 35,
34, 32, 21,
20, 18, 17
66.6 MHz - SDRAM Clocks w/serial config individual
enable/disable.
SDRAM
8, 10, 11,
12, 14, 15
33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
PCICLKs
Example:
a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively.
b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.
CLOCK
REF 0
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
IOAPIC (0:1)
14.31818 MHz
3
ICS9148-11
Technical Pin Function Descriptions
REF0
VDD(1,2,3)
The REF Output is a fixed frequency Clock that runs at the same
frequencyastheInputReferenceClockX1ortheCrystal(typically
14.31818MHz) attached across X1 and X2.
Thisisthepowersupplytotheinternalcorelogicofthedeviceaswell
astheclockoutputbuffersforREF(0:1), PCICLK, 48/24MHzA/B
andSDRAM(0:7).
PCICLK_F
Thispinoperatesat3.3Vvolts. Clocksfromthelistedbuffersthatit
supplieswillhaveavoltageswingfromGroundtothislevel. Forthe
actualguaranteedhighandlowvoltagelevelsfortheClocks,please
consult theDCparameter tableinthis datasheet.
ThisOutputisequaltoPCICLK(0:5)andisFREERUNNING, and
will not be stopped by PCI_STP#.
PCICLK(0:5)
TheseOutputClocksgenerateallthePCItimingrequirementsfora
Pentium/Pro based system. They conform to the current PCI
specification.Theyrunat1/2CPUfrequency.
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI output
buffers. Thevoltagelevelfortheseoutputsmaybe2.5or3.3volts.
Clocksfromthebuffersthateachsupplieswillhaveavoltageswing
fromGroundtothislevel. FortheactualGuaranteedhighandlow
voltage levels of these Clocks, please consult the DC parameter
tableinthisDataSheet.
MODE
ThisInputpinisusedtoselecttheInputfunctionofthe I/Opins. An
activeLowwillplacetheI/OpinsintheInputmodeandenablethose
stopclockfunctions.
GND
PWR_DWN#
Thisisthepowersupplyground(commonornegative)returnpinfor
theinternalcorelogicandalltheoutputbuffers.
ThisisanasynchronousactiveLowInputpinusedtoPowerDown
thedeviceintoaLowPowerstatebynotremovingthepowersupply.
The internal Clocks are disabled and the VCO and Crystal are
stopped. PoweredDownwillalsoplacealltheOutputsinalowstate
attheendoftheircurrentcycle. ThelatencyofPowerDownwillnot
begreaterthan3ms. TheI2CinputswillbeTri-Statedandthedevice
willretainallprogramminginformation.Thisinputpinonlyvalidwhen
MODE=0 (Power Management Mode)
X1
Thisinputpinservesoneoftwofunctions. Whenthedeviceisused
withaCrystal, X1actsastheinputpinforthereferencesignalthat
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. ThispinalsoimplementsaninternalCrystalloadingcapacitor
that is connected to ground. With a nominal value fo 33pF no
external load cap is needed for a CL=17 to 18pF crystal.
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLKclocksinanactivelowstate. AllotherClocksincluding
SDRAMclockswillcontinuetorunwhilethisfunctionisenabled.
The CPUCLKs will have a turn ON latency of at least 3 CPU
clocks.ThisinputpinonlyvalidwhenMODE=0(PowerManagement
Mode)
X2
This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
outputsignalthatdrives(orexcites)thediscreteCrystal. TheX2pin
willalsoimplementaninternalCrystalloadingcapacitornominally
33pF.
PCI_STOP#
ThisisasynchronousactiveLowInputpinusedtostopthePCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
ManagementMode)
CPUCLK(0:3)
These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
ClocksarecontrolledbytheVoltagelevelappliedtotheVDDL2pin
of the device. See the FunctionalityTable for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.
I2C
The SDATAand SCLOCK Inputs are use to program the device.
The clock generator is a slave-receiver device in the I2Cprotocol.
It will allow read-back of the registers. See configuration map for
registerfunctions. TheI2CspecificationinPhilipsI2CPeripherals
Data Handbook (1996) should be followed.
SDRAM(0:11)
TheseOutputClocksareusetodriveDynamicRAMsandarelow
skew copies of the CPU Clocks. The voltage swing of the
SDRAMsoutputiscontrolledbythesupplyvoltagethatisapplied
to VDD3 of the device, operates at 3.3 volts.
OE
Output Enable tristates the outputs when held low. This pin will
overridetheI2CByte0function, sothattheoutputswillbetristated
whentheOEislowregardlessoftheI2Cdefinedfunction.WhenOE
ishigh, theI2Cfunctionisin activecontrol.
IOAPIC (0:1)
This Output is a fixed frequency Output Clock that runs at the
ReferenceInput(typically14.31818MHz). Itsvoltagelevelswing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.
4
ICS9148-11
General I2C serial interface information
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,
with an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
Then Byte 0, 1, 2, etc in
sequence until STOP.
+ 8 bits dummy
command code
+ 8 bits dummy
Byte count
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
Clock Generator
Address (7 bits)
Byte 0
ACK
Byte 1
ACK
ACK
Byte 0, 1, 2, etc in sequence until STOP.
A(6:0) & R/W#
D3(H)
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H.
At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (Default=0)
BIT
Bit 7
Bit 6
PIN#
DESCRIPTION
PWD
-
-
-
Reserved
0
0
0
Must be 0 for normal operation
Must be 0 for normal operation
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
Must be 0 for normal operation
In Spread Spectrum, Controls Spreading
(0=1.8%, 1=0.6%)
Bit 5
Bit 4
0
0
0
-
Bit 3
Bit 2
Bit 1
Bit 0
-
-
Reserved
Reserved
0
0
Bit1
Bit0
1
1
0
0
1 - Tri-State
0
0
-
0 - Spread Spectrum Enable
1 - Testmode
0 - Normal operation
Note: PWD = Power-Up Default
5
ICS9148-11
Select Functions
OUTPUTS
SDRAM
FUNCTION
DESCRIPTION
PCI,
PCI_F
CPU
REF
IOAPIC
Tri - State
Test Mode
Hi-Z
TCLK/21
Hi-Z
TCLK/41
Hi-Z
TCLK/21
Hi-Z
TCLK1
Hi-Z
TCLK1
Notes:
1. REF is a test clock on the X1 inputs during test mode.
Byte 1: CPU Clock Register
Byte 2: PCICLK Clock Register
BIT PIN# PWD
DESCRIPTION
Reserved
BIT
PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
7
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Reserved
Bit 5 15
Bit 4 13
Bit 3 12
Bit 2 11
Bit 1 10
-
Reserved
-
Reserved
40
41
43
44
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 0
8
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4: SDRAM Clock Register
Byte 3: SDRAM Clock Register
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
1
1
1
1
1
1
1
1
SDRAM7 (Act/Inact)
Desktop only
SDRAM6 (Act/Inact)
Desktop only
SDRAM5 (Act/Inact)
Desktop only
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit 7
Bit 6
Bit 5
28
29
31
1
1
1
Reserved
Reserved
Reserved
Bit 3 17
Bit 2 18
Bit 1 20
Bit 0 21
SDRAM11 (Act/Inact)
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
32
34
35
37
38
1
1
1
1
1
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
6
ICS9148-11
Byte 6: Optional Register for Future
Byte 5: Peripheral Clock Register
BIT PIN# PWD DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
46
47
-
IOAPIC1 (Act/Inact)
IOAPIC0 (Act/Inact)
Reserved
-
Reserved
-
Reserved
2
REF0(Act/Inact)
Notes:
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Power Management
ClockEnableConfiguration
Other Clocks,
SDRAM,
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK
Crystal
VCOs
REF,
IOAPICs
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Stopped
Off
Off
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Low
33.3 MHz
Low
66.6 MHz
66.6 MHz
33.3 MHz
Fullclockcycletimingisguaranteedatalltimesafterthesystemhasinitiallypoweredupexceptwherenoted.Thefirstclockpulsecomingout
ofastoppedclockconditionmaybeslightlydistortedduetoclocknetworkchargingcircuitry. Boardroutingandsignalloadingmayhavea
largeimpactontheinitialclockdistortionalso.
ICS9148-11 Power Management Requirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free
running PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
1
1
1
PCI_STOP#
0 (Disabled)2
1 (Enabled)1
1
PWR_DWN#
1 (Normal Operation)3
0 (Power Down)4
3mS
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
7
ICS9148-11
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP#
issynchronizedbytheICS9148-11.TheminimumthattheCPUCLKisenabled(CPU_STOP#highpulse)is100CPUCLKs.Allotherclocks
willcontinuetorunwhiletheCPUCLKsaredisabled. TheCPUCLKswillalwaysbestoppedinalowstateandstartinsuchamannerthat
guaranteesthehighpulsewidthisafullpulse.CPUCLKonlatencyislessthan4CPUCLKsandCPUCLKofflatencyislessthan4CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside
the ICS9148-11.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-11. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP#issynchronizedbytheICS9148-11internally.TheminimumthatthePCICLK(0:5)clocksareenabled(PCI_STOP#highpulse)
is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.
PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawingshownonnextpage.)
8
ICS9148-11
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
Thepowerdownselectionisusedtoputthepartintoaverylowpowerstatewithoutturningoffthepowertothepart. PD#is anasynchronous
activelowinput.ThissignalissynchronizedinternalbytheICS9148-11priortoitscontrolactionofpoweringdowntheclocksynthesizer.
Internalclockswillnotberunningafterthedeviceisputinpowerdownstate. WhenPD#isactive(low)allclocksaredriventoalowstate
andheldpriortoturningoff theVCOsandtheCrystaloscillator.Thepoweronlatencyisguaranteedtobelessthan3mS.Thepowerdown
latency is less than three CPUCLK cycles. PCI_STOP# and CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
9
ICS9148-11
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . . . . . . 0°C to +70°C
StorageTemperature. . . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoselistedintheoperationalsectionsofthe
specificationsisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproductreliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IH
VDD+0.3
V
V
V
IL
VSS-0.3
0.8
5
A
µ
IIH
IIL1
IIL2
V = VDD
0.1
2.0
IN
A
µ
V = 0 V; Inputs with no pull-up resistors
-5
IN
A
µ
V = 0 V; Inputs with pull-up resistors
-200
-100
75
IN
IDD3.3OP CL = 0 pF; Select @ 66M
95
25
mA
Supply Current
Outputs Disabled
Supply Current
Input Capacitance1
IDD3.3OE CL = 0 pF; With input address to Vdd or GND
18
mA
CIN
Logic Inputs
X1 & X2 pins
5
pF
pF
CINX
27
36
5
45
Transition Time1
Settling Time1
Clk Stabilization1
Ttrans
Ts
To 1st crossing of target Freq.
3
ms
ms
From1st crossing to 1% target Freq.
From VDD = 3.3 Vto 1% target Freq.
TSTAB
5
3
ms
ps
TCPU-SDRAM2 VT = 1.5 V
200
500
Skew1
TCPU-PCI2 VT = 1.5 V
TREF-IOAPIC VT = 1.5 V
1
2
4
ns
ps
900
10
ICS9148-11
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
MIN
6
TYP
8
MAX UNITS
IDD2.5OP CL = 0 pF; Select @ 66M
9.5
mA
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
250
500
4
ps
Skew1
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
TREF-IOAPIC VT = 1.5 V; VTL = 1.25 V; CPU Leads
1
2
ns
ps
860
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
15
TYP
MAX UNITS
1
Output Impedance
RDSP2B
VO = VDD*(0.5)
45
45
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2B
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
15
2
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
2.6
0.3
-25
26
0.4
-16
V
mA
mA
VOL = 0.7 V
19
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.7
1.5
50
2
2
ns
ns
%
1
tf2 B
1
dt2B
55
1
tsk2B
VT = 1.25 V
60
250
250
150
+250
ps
ps
ps
ps
1
tjcyc-cyc2B VT = 1.25 V
150
30
1
Jitter
tj1s2B
VT = 1.25 V
VT = 1.25 V
1
tjabs2B
-250
80
1Guarenteed by design, not 100% tested in production.
11
ICS9148-11
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Output Impedance
RDSP4B
VO = VDD*(0.5)
30
30
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN4B
VO = VDD*(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
10
2
Ω
V
VOH4\B
VOL4B
IOH4B
IOL4B
2.4
0.45
-25
26
0.5
-16
V
mA
mA
19
40
1
Rise Time
Fall Time
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.2
1.6
1.6
60
ns
ns
%
ps
ps
ps
1
tf4 B
1
Duty Cycle
dt4B
54
1
tjcyc-cyc4B VT = 1.25 V
1400
300
800
1
Jitter
tj1s4B
VT = 1.25 V
VT = 1.25 V
400
1
tjabs4B
-1000
1000
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
RDSP7
RDSN7
VOH7
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
24
24
Ω
Ω
10
2.6
2.75
0.3
-62
50
V
VOL7
0.4
-54
V
IOH7
mA
mA
IOL7
VOL = 0.8 V
42
40
1
Rise Time
Fall Time
Tr7
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.9
0.9
2
2
ns
ns
%
ps
ps
ps
1
Tf7
1
Duty Cycle
Dt7
54
60
1
tjcyc-cyc7B VT = 1.25 V
1400
350
900
1
Jitter
tj1s7B
VT = 1.25 V
VT = 1.25 V
1
tjabs7B
-1000
1000
1Guarenteed by design, not 100% tested in production.
12
ICS9148-11
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
MAX UNITS
1
Output Impedance
RDSP1
VO = VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
Ω
V
VOH1
VOL1
IOH1
IOL1
2.6
3.1
0.15
-65
54
0.4
-54
V
mA
mA
40
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
50
2
ns
ns
%
ps
ps
ps
1
tf1
2
1
dt1
55
1
tsk1
VT = 1.5 V
200
10
500
150
250
1
Jitter
tj1s1
VT = 1.5 V
1
tjabs1
VT = 1.5 V
-250
65
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Output Impedance
RDSP3
VO = VDD*(0.5)
24
24
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
V
VOH3
VOL3
IOH3
IOL3
2.6
2.8
0.3
-67
55
0.4
-54
V
mA
mA
40
45
1
Rise Time
Fall Time
Duty Cycle
Skew
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
50
2
ns
ns
%
ps
ps
ps
1
Tf3
2
1
Dt3
55
1
Tsk3
VT = 1.5 V
200
50
500
150
250
1
Jitter
Tj1s3
VT = 1.5 V
1
Tjabs3
VT = 1.5 V
-250
100
1Guarenteed by design, not 100% tested in production.
13
ICS9148-11
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
A
A1
A2
B
AC
.625
.630
48
C
D
See Variations
E
.292
.296
.299
e
H
h
L
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9148F-11
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
14
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