ICS9148F-53 [ICSI]
Frequency Generator & Integrated Buffers for Mother Boards; 频率发生器和缓冲器集成的主机板
| 型号： | ICS9148F-53 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Mother Boards |
| 文件： | 总18页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-53
Frequency Generator & Integrated Buffers for Mother Boards
General Description
Features
The ICS9148-53 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro, AMD or Cyrix. Sixteen different reference
frequency multiplying factors are externally selectable with
smooth frequency transitions.
Generates the following system clocks:
-3CPU(2.5V/3.3V)upto150MHz.
-7PCI(3.3V)(includingonefree
running PCICLK)
-2AGP(3.3V)@2x PCI
-13SDRAMs(3.3V)upto150MHz
-1REF(3.3V)@14.318MHz
-1Fixedclock3.3V@48MHz
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-53
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Skew characteristics:
-CPUCPU<250ps
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation & I2C
programming for Power Management, Frequency Select
Efficient Power management scheme through power
down CPU, PCI,AGPand CPU_STOPclocks.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Uses external 14.318MHz crystal
48pin300milSSOP.
Block Diagram
Read back of FS pin values from I2C
Pin Configuration
Power Groups
VDD1=REF(0:1),X1,X2
VDD2=PCICLK_F,PCICLK(0:5)
VDD3=SDRAM(0:12), supplyforPLLcore
VDD4=AGP(1:2)
VDD5=FixedPLL,48MHz,AGP0
VDDL= CPUCLK(0:3)
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-53 Rev C 08/14/98
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-53
Pin Descriptions
PIN NUMBER
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
1
2
FS3
GND
X1
IN
PWR
IN
3,9,16,22,27,
33,39,45
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
5
6
X2
OUT
PWR
OUT
VDD2
PCICLK_F
7
FS11, 2
IN
PCICLK0
FS21, 2
OUT
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
8
10, 11, 12, 13, 47 PCICLK(1:5)
OUT
PWR
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
14
15
VDD5
BUFFERIN
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
CPU_STOP#
SDRAM 11
PCI_STOP#1
SDRAM 10
SDRAM (0:9)
IN
17
18
OUT
IN
OUT
OUT
28, 29, 31, 32, 34,
35,37,38
SDRAM clock outputs.
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
AGP_STOP#1
SDRAM9
PD#1
IN
20
OUT
IN
21
SDRAM8
VDD3
OUT
PWR
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
19,30,36
nominal 3.3V.
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
AGP0
OUT
25
26
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port output powered by VDD4.
Supply for AGP (0:2)
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
41, 43, 44
CPUCLK(0:3)
SDRAM12
VDDL
AGP1
VDD4
OUT
OUT
PWR
OUT
PWR
40
42
46
48
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-53
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
PD#
0
(INPUT)
SDRAM 8
(OUTPUT)
1
Power Management Functionality
AGP,
CPUCLK
Outputs
PCICLK_F,
REF, 48MHz
and SDRAM
PCICLK
(0:5)
Crystal
OSC
AGP_STOP# CPU_STOP# PCI_STOP#
VCO
AGP(1:2)
1
1
1
0
0
1
1
1
1
1
0
1
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
Running
Running
Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
3
ICS9148-53
Functionality
VDD1, 2, 3, 4=3.3V±5%, TA=0 to 70°C
Crystal(X1,X2)=14.31818MHz
CPU,SDRAM
(MHZ)
133
REF, IOAPIC
PCI (MHZ) AGP (MHZ) (MHZ)
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
44.33
41.33
50
88.67
82.67
100
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
124
150
140
105
112
115
120
100
46.67
35
93.33
70
37.33
38.33
40
74.67
76.66
80
33.3
31.75
33.3
30
66.6
63.5
66.6
60
95.25
83.3
75
75
37.5
34.25
33.4
30
75
68.5
66.8
60
68.5
66.8
60
4
ICS9148-53
General I2C serial interface information
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
Clock Generator
Address (7 bits)
Then Byte 0, 1, 2, etc in
sequence until STOP.
+ 8 bits dummy
command code
+ 8 bits dummy
Byte count
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
B.
The clock generator is a slave/receiver I2C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
Then Byte 0, 1, 2, etc. in
sequence until STOP.
Byte Count
Readback
ACK
ACK
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G.
The Fixed clocks 48MHz and 24MHz are not addressable in the registers for Stopping. These output are always running,
except in Tristate Mode.
H.
At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1
(Enabled output state).
5
ICS9148-53
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister(default=0)
Bit
Description
PWD
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
Bit (2, 6:4) CPU CLKs PCI CLKs AGP CLKs
Bit 7
0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
133
124
150
140
105
112
115
120
100
95.25
83.3
75
44.33
41.33
50
46.67
35
37.33
38.33
40
33.33
31.75
33.30
30.00
37.50
34.25
33.40
30.00
88.67
82.67
100
93.33
70
74.67
76.66
80
66.60
63.50
66.60
60.00
75.00
68.50
66.80
60.00
Bit
Note1
(2, 6:4)
75
68.5
66.8
60
0 - Frequency is selected by hardware select,
Bit 3
Latched Inputs
0
1 - Frequency is selected by Bit 6:4 (above)
0 - Normal
Bit 1
Bit 0
0
0
1 - Spread Spectrum Enabled (center spread)
0 - Running
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency;
Bits 2, 6:4 are default to 000
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
6
ICS9148-53
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
-
7
-
13
12
11
10
8
PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
40
-
41
43
44
PWD
D escription
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK 2 (Act/Inact)
CPUCLK 1 (Act/Inact)
CPUCLK 0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
25
-
26
-
PWD
Description
AGP0 (Active/Inactive)
(Reserved)
FS0#
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
1
1
-
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Byte 6: Optional Register for Possible
Furture Requirements
Bit
Pin #
-
8
7
47
-
2
46
2
PWD
1
-
Description
(Reserved)
FS2#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Pin #
PWD
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
-
FS1#
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
1
1
-
1
1
PCICLK5 (Act/Inact)
(Reserved)
FS3#
AGP1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for futue
applications.
7
ICS9148-53
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-53. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-53.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
8
ICS9148-53
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-53. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-53 internally.The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
9
ICS9148-53
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP (0:1) clocks. for low power
operation.AGP_STOP# is synchronized by theICS9148-53.TheAGP2 clock is free-running and is not affected byAGP_STOP#.
All other clocks will continue to run while theAGPCLKs are disabled. TheAGPCLKs will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and
AGPCLK off latency is less than 4AGPCLKs. This function is available only with MODE pin latched low.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-53.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
10
ICS9148-53
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Pins 2, 7, 8, 25 and 26 on the ICS9148-53 serve as dual signal
functions to the device. During initial power-up, they act as
input pins. The logic level (voltage) that is present on these
pins at this time is read and stored into a 4-bit internal data
latch. At the end of Power-On reset, (see AC characteristics
for timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
11
ICS9148-53
Fig. 2a
Fig. 2b
12
ICS9148-53
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; 66.8 MHz
-5
A
µ
IIL2
-200
-100
100
IDD3.3OP
160
mA
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
pF
ms
ms
ms
ns
CIN
Logic Inputs
5
45
2
CINX
Ttrans
Ts
X1 & X2 pins
27
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
TSTAB
2
4
TCPU-PCI1 VT = 1.5 V; f = 66/100 MHz; CPU leads
TCPU-PCI1 VT = 1.5 V; f = 83/75 MHz; CPU leads
TAGP-PCI1 VT = 1.5 V; f = 66.8 MHz; AGP Leads
TAGP-PCI1 VT = 1.5 V; f = 83.3 MHz; AGP Leads
TAGP-PCI1 VT = 1.5 V; f = 100 MHz; AGP Leads
1
1
2.4
3.8
4
ns
Skew1
500
600
450
600
700
550
ps
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP
CONDITIONS
CL = 0 pF; 66.8 MHz
MIN
TYP
10
MAX UNITS
20
mA
Supply Current
TCPU-PCI1 VT = 1.5 V; f = 66/100 MHz; CPU leads
TCPU-PCI1 VT = 1.5 V; f = 83/75 MHz; CPU leads
TAGP-PCI1 VT = 1.5 V; f = 66.8 MHz; AGP Leads
TAGP-PCI1 VT = 1.5 V; f = 83.3 MHz; AGP Leads
TAGP-PCI1 VT = 1.5 V; f = 100 MHz; AGP Leads
1
1
2.4
3.8
4
ns
ns
ps
ps
ps
4
Skew1
500
600
450
600
700
550
13
ICS9148-53
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2A
VOL2A
IOH2A
CONDITIONS
MIN
2.5
TYP
2.6
0.35
-29
37
MAX UNITS
V
IOH = -28 mA
IOL = 27 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-23
V
mA
mA
ns
IOL2A
33
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.1
50
2
1
Fall Time
tf2A
2
ns
1
Duty Cycle
dt2A
55
%
1
Skew
tsk2A
VT = 1.5 V
50
250
150
250
ps
1
Jitter, One Sigma
tj1s2A
VT = 1.5 V
65
ps
1
tjabs2A
VT = 1.5 V
Jitter, Absolute
-250
165
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
2
TYP
2.2
0.3
-20
26
MAX UNITS
V
VOH2B IOH = -8 mA
VOL2B
IOH2B
IOL2B
tr2B1
tf2B1
dt2B1
tsk2B1
I
OL = 12 mA
OH = 1.7 V
OL = 0.7 V
0.4
-16
V
mA
mA
ns
V
V
19
40
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.5
1.6
47
1.8
1.8
55
Fall Time
ns
Duty Cycle
%
Skew
VT = 1.25 V
60
250
ps
Jitter, Single Edge
Displacement2
Jitter, One Sigma
tjsed2B1
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
200
65
250
150
250
ps
ps
ps
Jitter, Absolute
-250
160
1 Guaranteed by design, not 100% tested in production.
2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
14
ICS9148-53
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Propagation Delay
Skew1
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-60
50
0.4
-40
V
IOH1
mA
mA
IOL1
41
45
Tr1
Tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.75
1.5
2
2
ns
ns
Dt1
Tprop
Tsk1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
50
55
6
%
4.2
ns
200
500
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-60
50
0.4
-40
V
mA
mA
ns
IOH1
IOL1
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.6
51
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
tj1s1a
tj1s1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
150
250
ps
ps
200
Jitter, Absolute1
tabs1a
tjabs1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-250
-650
135
500
250
650
ps
ps
1Guaranteed by design, not 100% tested in production.
15
ICS9148-53
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-60
50
0.4
-40
V
mA
mA
ns
IOH1
IOL1
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.4 V
1.1
1
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
49
55
250
3
%
1
Skew
Jitter, One Sigma1
tsk1
VT = 1.5 V
130
ps
tj1s1
VT = 1.5 V
2
%
Jitter, Absolute1
tabs1a
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-5
-6
2.5
4.5
5
6
%
%
tjabs1b
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP MAX UNITS
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
2.6
0.3
-32
25
2
V
V
VOL5
0.4
-22
IOH5
mA
mA
ns
IOL5
16
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
1
Fall Time
tf5
1.9
54
1
ns
1
Duty Cycle
dt5
45
-5
57
3
%
1
Jitter, One Sigma
tj1s5
VT = 1.5 V
%
1
tjabs5
VT = 1.5 V
Jitter, Absolute
-
5
%
1Guaranteed by design, not 100% tested in production.
16
ICS9148-53
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3:100pFceramic
All unmarked capacitors are 0.01µF ceramic
17
ICS9148-53
SYMBOL
COMMON DIMENSIONS
VAR IATION S
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
MAX.
.110
MIN. NOM. MAX.
A
A1
A2
B
AC
.620
.625
.630
48
.012
.016
.090
.092
.0135
.010
.010
C
-
D
E
See Variations
.296
0.025 BSC
.406
.013
.032
See Variations
5°
.093
.292
.299
48 pin SSOP Package
e
H
h
L
N
.400
.010
.024
.410
.016
.040
0°
.085
8°
.100
X
Ordering Information
ICS9148F-53
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
18
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