ICS9169C-273 [ICSI]
Frequency Generator for Pentium⑩ Based Systems; 频率发生器奔腾？基于系统
| 型号： | ICS9169C-273 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator for Pentium⑩ Based Systems |
| 文件： | 总8页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9169C-273
Frequency Generator for Pentium™ Based Systems
General Description
Features
•
•
•
•
Twelve selectable CPU clocks operate up to 83.3MHz
Maximum CPU jitter of ± 200ps
The ICS9169C-273 is a low-cost frequency generator
designed specifically for Pentium based chip set systems.
The integrated buffer minimizes skew and provides all the
clocks required. A 14.318 MHz XTAL crystal provides the
reference clock to generate standard Pentium frequencies.
The CPU clock makes gradual frequency transitions without
violating the PLL timing of internal microprocessor clock
multipliers.
Six BUS clocks support sync or async bus operation
250ps skew window for CPU outputs, 500ps skew
window for BUS outputs
CPU clocks BUS clocks skew 0-2ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU(1:6) outputs 2.5V(2.375-
2.62V)VDD option
32-pin SOJ package
Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
•
•
•
Twelve CPU clock outputs provide sufficient clocks for the
CPU, chip set, memory and up to two DIMM connectors (with
four clocks to each DIMM). Either synchronous (CPU/2) or
asynchronous (32 MHz) PCI bus operation can be selected
by latching data on the BSEL input.
•
•
•
48 MHz clock for USB support and 24 MHz clock for FD
Block Diagram
Pin Configuration
32-Pin SOJ
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
ADDRESS
CPU(1:12)
BUS (1:6)MHz
SELECT
FS2 FS1 FS0
(MHz)
VDD Groups:
48MHz 24MHz
REF
BSEL=1 BSEL=0
VDD1 = X1, X2, REF/BSEL
VDD2 = CPU(1:6)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
60
25
30
32
32
48
48
24
24
REF
REF
REF
REF
REF
REF
REF
VDD3 = CPU(7:12) & PLL Core
VDD4 = BUS(1:6)
VDD5 = 48/24 MHz
66.6
REF/2
55
33.3
REF/4
27.5
37.5
41.7
32
48
24
REF/3
32
REF/2
48
REF/4
24
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
L4 = FS2
75
32
48
24
83.3
Tristate
32
48
24
Tristate Tristate Tristate Tristate Tristate
Pentium is a trademark on Intel Corporation.
9169C-273RevC031897
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9169C-273
Pin Descriptions
PIN NUMBER
PIN NAME
VDD1
TYPE
DESCRIPTION
1
PWR
Power for device logic, and 24/48MHz output
XTAL or external reference frequency input. This input
includes XTAL load capacitance and feedback bias for a
12-16MHz crystal, nominally 14.31818MHz external crystal
load of 30pF to GND recommended for VDD power on faster
than 2.0ms.
2
X1
IN
XTAL output which includes XTAL load capacitance.
External crystal load of 10pF to GND recommended for VDD
power on faster than 2.0ms.
3
X2
OUT
4,11,20,26
GND
PWR
OUT
Ground for device logic.
Processor clock output which is a multiple of the input
reference frequency.
CPU(1)
5
FS0
IN
Frequency multiplier select pin. See shared pin description.*
CPU
(2:5) (8:12)
Processor clock outputs which are a multiple of the input
reference frequency.
6,7,9,10,15,16,17,18,19
8
OUT
PWR
Power for CPU(1:6) output buffers only. Can be reduced VDD
for 2.5V (2.375-2.62V) next generation processor clocks.
VDD2
CPU(6)
FS1
Processor clock output which is a multiple of the input
reference frequency internal pull up devices.
OUT
IN
12
13
Frequency multiplier select pin. See shared pin description.*
Processor clock output which is a multiple of the input
reference frequency internal pull up devices.
CPU(7)
FS2
OUT
IN
Frequency multiplier select pin. See shared pin description.*
Power for CPU(7:12) output buffers. Must be nominal
3.3V (3.0 to 3.7V)
14
VDD3
PWR
BUS clock outputs which are a multiple of the input reference
clock.
28, 27, 25, 24, 22, 21
BUS (1:6)
OUT
23
29
VDD4
VDD5
PWR
PWR
Power for BUS clock buffers BUS(1:6).
Power for fixed clock buffer (48 MHz, 24 Mhz).
Fixed 24MHz clock (assuming a 14.31818MHz REF
frequency).
30
31
24MHz
48MHz
REF
OUT
OUT
OUT
Fixed 48MHz clock (assuming a 14.31818MHz REF
frequency).
Fixed 14.31818MHz clock (assuming a 14.31818MHz REF
frequency).
32
Selection for synchronous or asynchronous bus clock
operation. See shared pin programming description late in this
data sheet for further explanation.
BSEL
IN
* The internal pull-up will vary from 350K to 500K based on temperature.
2
ICS9169C-273
Shared Pin Operation -
Input/Output Pins
Test Mode Operation
The ICS9169C-273 includes a production test verification
mode of operation. This requires that the FSO and FS1 pins
be programmed to a logic high and the FS2 pin be
programmedtoalogiclow(seeSharedPinOperationsection).
In this mode the device will output the following
frequencies.
Shared Pin Operation - Input/Output Pins 5, 12, 13 and 32
on the ICS9169C-273 serve as dual signal functions to the
device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at
this time is read and stored into a 4-bit internal data latch.
At the end of Power-On reset, (see AC characteristics for
timing values), the device changes the mode of operation
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
Pin
Frequency
REF
REF/2
REF/4
REF2
REF/4
REF/3
REF
48MHz
24MHz
CPU (1:12)
To program (load) the internal configuration register for
these pins, a resistor is connected to either theVDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
BSEL=1
BSEL = 0
BUS (1:6)
Note: REF is the frequency of either the crystal connected
between the devices X1and X2 or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Figures 1 and 2 show the recommended PCB means of
implementing this function. In Fig. 1 either one of the
resistors is stuffed on the board (selective stuffing) to
configure the device’s internal logic. Figures 2a and b
provide a single resistor stuffing option where either
solder spot tabs or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
(Resistors are surface mount devices
shown schematically between 5.m. pads)
*use only one programming resistor
Fig. 1
3
ICS9169C-273
Fig. 2b
Fig. 2a
Fig. 3
4
ICS9169C-273
Technical Pin Function Descriptions
VDD1
clocks is controlled by the supply that is applied to the
VDD pin of the group. See the Functionality Table at the
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. Fixed clock output buffers
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
CPUL, BUS & SDRAM pins. See the Funtionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies. The
device reads these pins at power-up and stores the
programmed selection code in an internal data latch. (See
programming section of this data sheet for configuration
circuitry recommendations.
This pin may be operated at any voltage between 3.0 and
5.5 volts. Clocks from the listed buffers that it supplies
will have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
GND
This is the power supply ground return pin for the internal
logic of the device as well as the following Clock Output
buffers:
BSEL
When this pin is a logic 1, it will place the CPU clocks in
the synchronous mode (running at half the frequency of
the Ref). If this pin is a logic 0, it will be in the asynchronous
mode for the CPU clocks and will operate at the
preprogrammed fixed frequency rate. It is a shared pin
and is programed the same way as the frequency select
pins.
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
D. Fixed clock output buffers
E. 24/48MHz clock output buffers
VDD (2:3)
X1
These are the power supply pins for the CPU (1:6) and
CPU (7:12) clock buffers. By separating the clock power
pins, each group can receive the appropriate power
decoupling and bypassing necessary to minimize EMI
and crosstalk between the individual signals. VDD2 can
be reduced to 2.5V VDD for advanced processor clocks,
which will bring CPU (1:6) outputs at 0 to 2.5V output
swings.
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, X1 is the device’ input
pin for that reference clock. This pin also implements an
internal crystal loading capacitor that is connected to ground.
See the data tables for the value of the capacitor.
X2
VDD4
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is
an output signal that drives (or excites) the discrete crystal.
This pin also implements an internal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
This is the power supply pin for BUS clock buffers
BUS (1:6).
VDD5
This is the power supply pin for fixed clock buffer (48MHz
and 24MHz).
CPU (1:12)
48 MHz
These pins are clock outputs that drive the processor and
other CPU related circuitry that require clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these clocks is controlled by that which is applied
to the VDD pins of the device. See note on VDD3. See the
Functionality Table at the beginning of this data sheet for
a list of the specific frequencies that this clock operates at
and the selection codes that are necessary to produce
these frequencies.
This is a fixed frequency clock that is typically used to
drive Super I/O peripheral device needs.
24 MHz
This is a fixed frequency clock that is typically used to
drive Keyboard controller clock needs.
REF
This is a fixed frequency clock that runs at the same
frequency as the input reference clock (typically 14.31818
MHz) is and typically used to drive Video and ISA BUS
requirements.
BUS (1:6)
These pins are the Clock Outputs that are intended to drive
the systems plug-in card bus. The voltage swing of these
5
ICS9169C-273
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5V to VDD +0.5V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current1
Output High Current1
Output Low Current1
Output High Current1
Output Low Voltage1
Output High Voltage1
Output Low Voltage1
Output High Voltage1
Supply Current
SYMBOL
TEST CONDITIONS
MIN
-
TYP
-
MAX
UNITS
V
IL
V
DD
0.2V
IH
V
DD
0.7V
-28.0
-5.0
16.0
-
-
-
-
V
IL
I
IN
V
= 0V
= V
-10.5
-
µA
µA
mA
mA
mA
mA
V
IH
IN
V
DD
I
5.0
-
OL
I
OL
V
= 0.8V; for CPU, BUS, Fixed CLKs
= 2.0V; for CPU, BUS, Fixed CLKs
OL
= 0.8V; for REF CLK
25.0
-30.0
30.0
-38.0
0.3
2.8
0.3
2.8
90
OH
I
OL
V
-14
-
OL
I
V
19.0
-
OH
I
OL
= 2.0V; for REF CLK
V
-16.0
0.4
-
OL
V
OL
I
= 8mA; for CPU, BUS, Fixed CLKs
= -8mA; for CPU, BUS, Fixed CLKs
OL
= 10mA; for REF CLK
-
OH
V
OH
I
2.4
-
V
OL
V
I
0.4
-
V
OH
V
OH
= -15mA; for REF CLK
I
2.4
-
V
DD
I
@66.6 MHz; all outputs unloaded
180
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS9169C-273
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
AC Characteristics
PARAMETER
Rise Time1
SYMBOL
Tr1
TEST CONDITIONS
20pF load, 0.8 to 2.0V
CPU & BUS
20pF load, 2.0 to 0.8V
CPU & BUS
20pF load, 20% to 80%
CPU & BUS
MIN
TYP
0.9
0.8
1.5
1.4
50
MAX
1.5
UNITS
ns
-
-
Fall Time1
Tf1
1.4
ns
Rise Time1
Tr2
-
2.5
ns
20pF load, 80% to 20%
CPU & BUS
Fall Time1
Tf2
-
2.4
ns
Duty Cycle1
Jitter, One Sigma1
Dt
20pF load @ VOUT=1.4V
45
-
60
%
CPU & BUS Clocks; Load=20pF,
BSEL=1
Tj1s1
50
150
ps
CPU & BUS Clocks; Load=20pF,
BSEL=1
Jitter, Absolute1
Tjab1
Tj1s2
Tjab2
Fi
-250
-
1
250
3
ps
%
Jitter, One Sigma1
Jitter, Absolute1
REF & Fixed CLK; Load=20pF
REF & Fixed CLK; Load=20pF
-
-5
2
5
%
Input Frequency1
Logic Input Capacitance1
Crystal Oscillator Capacitance1
Power-on Time1
Clock Skew1
12.0
14.318
5
16.0
-
MHz
pF
pF
ms
ps
CIN
Logic input pins
X1, X2 pins
-
-
CINX
ton
18
-
From VDD=1.6V to 1st crossing of
66.6 MHz VDD supply ramp < 40ms
-
2.5
150
150
1.0
4.5
250
250
2
Tsk1
Tsk2
Tsk3
CPU to CPU; Load=20pF; @1.4V
-
Clock Skew1
BUS to BUS; Load=20pF; @1.4V
-
ps
CPU to BUS; Load=20pF; @1.4V
(CPU is early)
Clock Skew1
0
ns
CPU (@3.3V) to CPU (@2.5V)
(2.5V CPU is late)
Clock Skew1
TSR4
0.5
1
ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS9169C-273
0.818
SOIC Package
Ordering Information
ICS9169CM-273
SOJ Package
ICS9169CJ-273
Example:
ICS XXXX M- PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
J=SOJ
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
8
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