ICS9169CF-41 [ICSI]

Frequency Generator for PentiumPro⑩ Based Systems; 频率发生器PentiumPro ™的系统


型号：	ICS9169CF-41
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Frequency Generator for PentiumPro⑩ Based Systems 频率发生器PentiumPro ™的系统
文件：	总7页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Integrated

Circuit

Systems, Incꢀ

ICS9169C-41

Frequency Generator for PentiumPro™ Based Systems

General Description

Features

•

12 selectable CPU/SDRAM/AGP clocks up to 75 MHz

Six PCI clocks, synchronous or asynchronous mode, pin

selectable by Bus Select input (pin 19)

The ICS9169C-41 is a Clock Synthesize/Driver chip for

Pentium, PentiumPro or Cyrix 68x86 based motherboards

using SDRAM.

•

One USB clock at 48MHz, meets Intel jitter, accuracy, as

well as rise and fall time requirements

Features include four dual purpose I/O pins which provide

extra CPU clocks and enable the part to be packaged in a

low-cost 34-pin SSOP package. These four pins latch the

select inputs at the internal Power-On Reset. Additionally,

the device meets the Pentium and PentiumPro power-up

stabilization, which requires that CPU and PCI clocks be

stable within 2ms after power-up.

•

One I/O clock at 24MHz

Two Ref. Clocks at 14.318MHz

CPU clocks to PCI clock skew of 1-4ns (CPU early)

Low CPU and PCI clock jitter <200ps

Low skew outputs, skew window 250ps for CPU clocks

and for PCI clocks

Improved output drivers are designed for low EMI

Test Mode

3.3V ±10% operation

The ICS9169C-41 clock outputs are designed for low EMI

emissions. Controlled rise and fall times, unique output

driver circuits and innovative circuit layout techniques enable

the ICS9169C-41 to have lower EMI than other clock

devices.

•

Space saving and low cost 34-pin SSOP package

The ICS9169C-41 accepts a 14.318MHz reference crystal or

clock as its input and runs from a 3.3V supply.

Block Diagram

Pin Configuration

34-Pin SSOP

Pentium is a trademark on Intel Corporation.

9169-41RevD5/02/00

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9169C-41

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

PWR

DESCRIPTION

1, 8, 14, 26

V_DD

Voltage Supply

Crystal input. Nominally 14.318MHz

Crystal output. Nominally 14.318MHz

Ground

OUT

PWR

4, 11 20, 23, 29

GND

Processor clock output which are a multiple of the input reference

clock as shown in the preceding table.

CPUCLK1

FS2

OUT

Frequency multiplier select pins. See shared pin programming

description later in this data sheet for further explanation.

18, 17, 13, 12,

10, 9, 7, 6,

CPUCLK(11,10,7:2)

CPUCLK8

FS1

OUT

CPU clock output

Processor clock output which are a multiple of the input reference

clock as shown in the preceding table.

Frequency multiplier select pin. See shared pin programming

description later in this data sheet for further explanation.

Processor clock output which are a multiple of the input reference

clock as shown in the preceding table.

CPUCLK9

FS0

OUT

Frequency multiplier select pins. See shared pin programming

description later in this data sheet for further explanation.

Processor clock output which are a multiple of the input reference

clock as shown in the preceding table.

CPUCLK12

OUT

Selection for synchronous (High) or asynchronous (Low) bus clock

operation. See shared pin programming description later in this data

sheet for further explanation.

BSEL

28, 27, 25, 24, 22, 21

PCICLK (6:1)

USBCLK

IOCLK

OUT

PWR

OUT

PCI Clock outputs. syncronous to CPU with 1-4ns delay.

USB clock output 48 MHz

I/O clock output 24 MHz

AVDD

Analog Voltage Supply

REF1

Reference clock output (14.318 MHz)

Reference clock output (14.318 MHz) for ISA slots

(drives C_LOAD= 45pF)

REF0

OUT

ICS9169C-41

Functionality

3.3V±10%, 0-70^°C

Crystal (X1, X2) = 14.31818 MHz

PCICLK(1-5) PCICLK(1-5)

FS2 FS1 FS0

XTALIN

CPUCLK

REF(0-1)

USBCLK

IOCLK

BSEL = 1

BSEL = 0

14.318MHz

TCLK⁽¹⁾

33.33MHz

75.0MHz

55.0MHz

HI-Z

16.67MHz

32MHz

14.318MHz

HI-Z

48MHz

HI-Z

24MHz

HI-Z

37.5MHz

27.5MHz

HI-Z

32MHz

HI-Z

50.0MHz

66.67MHz

60.0MHz

TCLK/2⁽²⁾

25.0MHz

33.33MHz

30.0MHz

TCLK/4

32MHz

TCLK/3

14.318MHz

TCLK

48MHz

TCLK/2

24MHz

TCLK/4

Notes

1. TCLK is supplied on XTALIN pin

2. Bidirectional CPUCLK I/O pins are high in test mode.

ICS9169C-41

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Electrical Characteristics at 3.3V

V_DD= 3.0 – 3.7V, T_A= 0 –70°C unless otherwise stated

DC Characteristics

PARAMETER

Input Low Voltage

Input High Voltage

Input Low Current

Input High Current

Output Low Current¹

Output High Current¹

Output Low Current¹

Output High Current¹

Output Low Voltage¹

Output High Voltage¹

Output Low Voltage¹

Output High Voltage¹

Supply Current

SYMBOL

V_IL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

0.2V_DD

V_IH

I_IL

0.7V_DD

VIN=0V

VIN=V_DD

-28.0

-10.5

µA

I_IH

-5.0

5.0

I_OL

VOL=0.8V; for CPU, PCI, REF CLKS

VOL=2.0V; for CPU, PCI, REF CLKS

VOL=0.8V; for Fixed CLK

16.0

25.0

-30.0

30.0

-38.0

0.3

2.8

0.3

2.8

I_OH

I_OL

19.0

-14.0

I_OH

V_OL

V_OH

V_OL

V_OH

I_DD

VOL=2.0V; for Fixed CLK

-16.0

0.4

IOL=8mA; for CPU, PCI, REF

IOH=-8mA; for CPU, PCI, REF

IOL=18mA; Fixed CLK's

2.4

0.4

IOH=-18mA; Fixed CLK's

2.4

@66.6 MHz; all outputs unloaded

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9169C-41

Electrical Characteristics at 3.3V

V_DD= 3.0 – 3.7V, T_A= 0 –70°C unless otherwise stated

AC Characteristics

PARAMETER

Rise Time¹

Fall Time¹

Rise Time¹

Fall Time¹

SYMBOL

Tr1

TEST CONDITIONS

20pF load, 0.8 to 2.0V; All Except Ref

20pF load, 2.0 to 0.8V; All Except Ref

30pF load, 0.8 - 2.0V All Except Ref

30pF load, 2.0 - 0.8V All Except Ref

45pF; 0.8 - 2.0V; Ref only

45pF; 2.0 - 0.8V; Ref only

20, 30, 45pF load @ VOUT=1.5V

CPU & PCI Clocks

MIN

TYP

0.9

0.8

1.3

1.7

1.0

MAX

1.2

1.6

2.0

UNITS

Tf1

Tr2

Tf2

Rise Time

Tr3

Fall Time

Tf3

Duty Cycle¹

Jitter, One Sigma¹

Jitter, Absolute¹

Jitter, One Sigma¹

Jitter, Absolute¹

Tj1s1

Tjab1

Tj1s2

Tjab2

150

250

CPU & PCI Clocks (@ 60 & 66MHz)

Ref & Fixed CLKs

-250

Ref & Fixed CLKs

1.0

290

4.5

14.318

2.5

350

CPU Outputs

Jitter - Cycle to Cycle

Tcc

Fixed Clocks & REF0

12.0

Input Frequency¹

Logic Input Capacitance¹

16.0

MHz

CIN

Logic input pins

X1, X2 pins

Crystal Oscillator

Capacitance¹

CINX

ton

From VDD=1.6V to 1st crossing of 66.6 MHz

VDD supply ramp < 40ms

Power-on Time¹

1.9

2.0

From 1st crossing of acquisition to

<1% settling

Frequency Settling Time¹

Clock Skew¹(window)

2.0

188

1.2

4.0

300

4.0

Tsk1

Tsk2

CPU to CPU & PCI - PCI; Same Load; @1.5V

CPU(20pF) - PCI (30pF); @1.5V (CPU is

Early)

1.0

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9169C-41

Technical Pin Function Descriptions

VDD

PCICLK

Clock output driver for the PCI Bus.

This is the power supply to the internal logic of the device as

well as the following clock output buffers:

FS0, FS1, FS2

This pin may be operated at any voltage between 3.0 and 3.7

volts. Clocks from the listed buffers that it supplies will

have a voltage swing from ground to this level. For the

actual guaranteed high and low voltage levels of these clocks,

please consult the AC parameter table in this data sheet.

These pins control the frequency of the clocks at the CPU,

BUS and SDRAM pins. See the Funtionality table at the

beginning of this data sheet for a list of the specific

frequencies that these clock operate at and the selection

codes that are necessary to produce these frequencies. The

device reads these pins at power-up and stores the

programmed selection code in an internal data latch. If a "1"

value is desired for a specific frequency selection bit,a 10K

ohm resistor must be connected from the appropriate FS pin

to the VDD supply. If a "O" value is desired, then the 10K

resistor must be connected to ground. After the internal

power On reset latches the input data, these pins become

output clocks and no further frequency selection is possible.

GND

This is the power supply ground return pin.

This pin serves one of two functions. When the device is

used with a crystal, X1 acts as the input pin for the reference

signal that comes from the discrete crystal. When the device

is driven by an external clock signal, X1 is the device input

pin for that reference clock. This pin also implements an

internal crystal loading capacitor that is connected to ground.

See the data tables for the value of the capacitor.

48MHz

This is a fixed frequency clock that is typically used to drive

USB peripheral device needs.

24MHz

This pin is used only when the device uses a Crystal as the

reference frequency source. In this mode of operation, X2 is

an output signal that drives (or excites) the discrete crystal.

This pin also implements an internal crystal loading capacitor

that is connected to ground. See the data tables for the value

of the capacitor.

This is a fixed frequency clock that is typically used to drive

super I/O peripheral device needs.

REF (0:1)

This is a fixed frequency clock that runs at the same frequency

as the input freerence clock (typically 14.31818 MHz) is

and typically used to drive Video and ISABUS requirements.

CPU (1:12)

These pins are the clock output that drive the processor and

other CPU related circuitry that require clocks which are in

tight skew tolerance with the CPU clock. See the

Functionality table at the beginning of this data sheet for a

list of the specific frequencies that these clocks operate at

and the selection codes that are necessary to produce these

frequencies. Some of these pin serve dual functions.

ICS9169C-41

Ordering Information

ICS9169CF-41

Example:

ICS XXXX F - PPP

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9169CF-41 [ICSI]

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