ICS9169CF-PPP [IDT]
Processor Specific Clock Generator, 75MHz, PDSO34, 0.300 INCH, SSOP-34;型号: | ICS9169CF-PPP |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Processor Specific Clock Generator, 75MHz, PDSO34, 0.300 INCH, SSOP-34 光电二极管 |
文件: | 总7页 (文件大小:152K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS9169C-41
Frequency Generator for PentiumPro™ Based Systems
General Description
Features
•
•
12 selectable CPU/SDRAM/AGP clocks up to 75 MHz
Six PCI clocks, synchronous or asynchronous mode, pin
selectable by Bus Select input (pin 19)
The ICS9169C-41 is a Clock Synthesize/Driver chip for
Pentium, PentiumPro or Cyrix 68x86 based motherboards
using SDRAM.
•
One USB clock at 48MHz, meets Intel jitter, accuracy, as
well as rise and fall time requirements
Features include four dual purpose I/O pins which provide
extra CPU clocks and enable the part to be packaged in a
low-cost 34-pin SSOP package. These four pins latch the
select inputs at the internal Power-On Reset. Additionally,
the device meets the Pentium and PentiumPro power-up
stabilization, which requires that CPU and PCI clocks be
stable within 2ms after power-up.
•
•
•
•
•
One I/O clock at 24MHz
Two Ref. Clocks at 14.318MHz
CPU clocks to PCI clock skew of 1-4ns (CPU early)
Low CPU and PCI clock jitter <200ps
Low skew outputs, skew window 250ps for CPU clocks
and for PCI clocks
Improved output drivers are designed for low EMI
Test Mode
3.3V ±10% operation
The ICS9169C-41 clock outputs are designed for low EMI
emissions. Controlled rise and fall times, unique output
driver circuits and innovative circuit layout techniques enable
the ICS9169C-41 to have lower EMI than other clock
devices.
•
•
•
•
Space saving and low cost 34-pin SSOP package
The ICS9169C-41 accepts a 14.318MHz reference crystal or
clock as its input and runs from a 3.3V supply.
Block Diagram
Pin Configuration
34-Pin SSOP
Pentium is a trademark on Intel Corporation.
9169-41RevD5/02/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9169C-41
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
PWR
IN
DESCRIPTION
1, 8, 14, 26
VDD
X1
Voltage Supply
2
Crystal input. Nominally 14.318MHz
Crystal output. Nominally 14.318MHz
Ground
3
X2
OUT
PWR
4, 11 20, 23, 29
GND
Processor clock output which are a multiple of the input reference
clock as shown in the preceding table.
CPUCLK1
FS2
OUT
IN
5
Frequency multiplier select pins. See shared pin programming
description later in this data sheet for further explanation.
18, 17, 13, 12,
10, 9, 7, 6,
CPUCLK(11,10,7:2)
CPUCLK8
FS1
OUT
OUT
IN
CPU clock output
Processor clock output which are a multiple of the input reference
clock as shown in the preceding table.
15
16
Frequency multiplier select pin. See shared pin programming
description later in this data sheet for further explanation.
Processor clock output which are a multiple of the input reference
clock as shown in the preceding table.
CPUCLK9
FS0
OUT
IN
Frequency multiplier select pins. See shared pin programming
description later in this data sheet for further explanation.
Processor clock output which are a multiple of the input reference
clock as shown in the preceding table.
CPUCLK12
OUT
19
Selection for synchronous (High) or asynchronous (Low) bus clock
operation. See shared pin programming description later in this data
sheet for further explanation.
BSEL
IN
28, 27, 25, 24, 22, 21
PCICLK (6:1)
USBCLK
IOCLK
OUT
OUT
OUT
PWR
OUT
PCI Clock outputs. syncronous to CPU with 1-4ns delay.
USB clock output 48 MHz
30
31
32
33
I/O clock output 24 MHz
AVDD
Analog Voltage Supply
REF1
Reference clock output (14.318 MHz)
Reference clock output (14.318 MHz) for ISA slots
(drives CLOAD = 45pF)
34
REF0
OUT
2
ICS9169C-41
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
PCICLK(1-5) PCICLK(1-5)
FS2 FS1 FS0
XTALIN
CPUCLK
REF(0-1)
USBCLK
IOCLK
BSEL = 1
BSEL = 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
14.318MHz
TCLK(1)
33.33MHz
75.0MHz
55.0MHz
HI-Z
16.67MHz
32MHz
14.318MHz
14.318MHz
14.318MHz
HI-Z
48MHz
48MHz
48MHz
HI-Z
24MHz
24MHz
24MHz
HI-Z
37.5MHz
27.5MHz
HI-Z
32MHz
32MHz
HI-Z
50.0MHz
66.67MHz
60.0MHz
TCLK/2(2)
25.0MHz
33.33MHz
30.0MHz
TCLK/4
32MHz
32MHz
32MHz
TCLK/3
14.318MHz
14.318MHz
14.318MHz
TCLK
48MHz
48MHz
48MHz
TCLK/2
24MHz
24MHz
24MHz
TCLK/4
Notes
1. TCLK is supplied on XTALIN pin
2. Bidirectional CPUCLK I/O pins are high in test mode.
3
ICS9169C-41
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current1
Output High Current1
Output Low Current1
Output High Current1
Output Low Voltage1
Output High Voltage1
Output Low Voltage1
Output High Voltage1
Supply Current
SYMBOL
VIL
TEST CONDITIONS
MIN
TYP
-
MAX
UNITS
V
-
0.2VDD
VIH
IIL
0.7VDD
-
-
-
V
VIN=0V
VIN=VDD
-28.0
-10.5
-
µA
µA
mA
mA
mA
mA
V
IIH
-5.0
5.0
-
IOL
VOL=0.8V; for CPU, PCI, REF CLKS
VOL=2.0V; for CPU, PCI, REF CLKS
VOL=0.8V; for Fixed CLK
16.0
25.0
-30.0
30.0
-38.0
0.3
2.8
0.3
2.8
75
IOH
IOL
-
19.0
-
-14.0
-
IOH
VOL
VOH
VOL
VOH
IDD
VOL=2.0V; for Fixed CLK
-16.0
0.4
-
IOL=8mA; for CPU, PCI, REF
IOH=-8mA; for CPU, PCI, REF
IOL=18mA; Fixed CLK's
-
2.4
-
V
0.4
-
V
IOH=-18mA; Fixed CLK's
2.4
-
V
@66.6 MHz; all outputs unloaded
95
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS9169C-41
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
AC Characteristics
PARAMETER
Rise Time1
Fall Time1
Rise Time1
Fall Time1
SYMBOL
Tr1
TEST CONDITIONS
20pF load, 0.8 to 2.0V; All Except Ref
20pF load, 2.0 to 0.8V; All Except Ref
30pF load, 0.8 - 2.0V All Except Ref
30pF load, 2.0 - 0.8V All Except Ref
45pF; 0.8 - 2.0V; Ref only
45pF; 2.0 - 0.8V; Ref only
20, 30, 45pF load @ VOUT=1.5V
CPU & PCI Clocks
MIN
TYP
0.9
0.8
1.3
1.3
1.7
1.0
50
MAX
1.2
1.2
1.6
1.6
2.0
2.0
55
UNITS
ns
-
Tf1
-
ns
Tr2
-
ns
Tf2
-
ns
Rise Time
Tr3
-
ns
Fall Time
Tf3
-
ns
Duty Cycle1
Jitter, One Sigma1
Jitter, Absolute1
Jitter, One Sigma1
Jitter, Absolute1
Dt
45
%
Tj1s1
Tjab1
Tj1s2
Tjab2
-
50
150
250
3
ps
CPU & PCI Clocks (@ 60 & 66MHz)
Ref & Fixed CLKs
-250
-
ps
-
1
%
Ref & Fixed CLKs
-
1.0
290
4.5
14.318
5
2.5
350
6
%
CPU Outputs
-
ps
Jitter - Cycle to Cycle
Tcc
Fixed Clocks & REF0
-
12.0
-
%
Input Frequency1
Logic Input Capacitance1
Fi
16.0
-
MHz
pF
CIN
Logic input pins
X1, X2 pins
Crystal Oscillator
Capacitance1
CINX
ton
-
-
18
-
pF
From VDD=1.6V to 1st crossing of 66.6 MHz
VDD supply ramp < 40ms
Power-on Time1
1.9
2.0
ms
From 1st crossing of acquisition to
<1% settling
Frequency Settling Time1
Clock Skew1 (window)
Clock Skew1 (window)
ts
-
-
2.0
188
1.2
4.0
300
4.0
ms
ps
Tsk1
Tsk2
CPU to CPU & PCI - PCI; Same Load; @1.5V
CPU(20pF) - PCI (30pF); @1.5V (CPU is
Early)
1.0
ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
5
ICS9169C-41
Technical Pin Function Descriptions
VDD
PCICLK
Clock output driver for the PCI Bus.
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
FS0, FS1, FS2
This pin may be operated at any voltage between 3.0 and 3.7
volts. Clocks from the listed buffers that it supplies will
have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these clocks,
please consult the AC parameter table in this data sheet.
These pins control the frequency of the clocks at the CPU,
BUS and SDRAM pins. See the Funtionality table at the
beginning of this data sheet for a list of the specific
frequencies that these clock operate at and the selection
codes that are necessary to produce these frequencies. The
device reads these pins at power-up and stores the
programmed selection code in an internal data latch. If a "1"
value is desired for a specific frequency selection bit,a 10K
ohm resistor must be connected from the appropriate FS pin
to the VDD supply. If a "O" value is desired, then the 10K
resistor must be connected to ground. After the internal
power On reset latches the input data, these pins become
output clocks and no further frequency selection is possible.
GND
This is the power supply ground return pin.
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, X1 is the device input
pin for that reference clock. This pin also implements an
internal crystal loading capacitor that is connected to ground.
See the data tables for the value of the capacitor.
48MHz
This is a fixed frequency clock that is typically used to drive
USB peripheral device needs.
X2
24MHz
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is
an output signal that drives (or excites) the discrete crystal.
This pin also implements an internal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
This is a fixed frequency clock that is typically used to drive
super I/O peripheral device needs.
REF (0:1)
This is a fixed frequency clock that runs at the same frequency
as the input freerence clock (typically 14.31818 MHz) is
and typically used to drive Video and ISABUS requirements.
CPU (1:12)
These pins are the clock output that drive the processor and
other CPU related circuitry that require clocks which are in
tight skew tolerance with the CPU clock. See the
Functionality table at the beginning of this data sheet for a
list of the specific frequencies that these clocks operate at
and the selection codes that are necessary to produce these
frequencies. Some of these pin serve dual functions.
6
ICS9169C-41
Ordering Information
ICS9169CF-41
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
7
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