ICS9248-50_1 [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248-50_1 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总10页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-50
Integrated
Circuit
Systems, Inc.
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9248-50
Features
•
Generates the following system clocks:
- 2 CPU (2.5V) up to 100MHz.
- 6 PCI (3.3V) @ 33.3MHz (Includes one free
running).
- 2 REF clks (3.3V) at 14.318MHz.
Skew characteristics:
•
- CPU – CPU<175ps
- PCI – PCI < 500ps
- CPU(early) – PCI = 1.5ns – 4ns.
ICS9248-50
•
•
•
•
Supports Spread Spectrum modulation for CPU and
PCI clocks, 0.5% down spread
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin (209 mil) SSOP package
Block Diagram
Pin Configuration
28-Pin SSOP
Power Groups
0278I—06/03/03
ICS9248-50
Pin Descriptions
Pin number
Pin name
GNDREF
X1
Type
Description
1
Power Ground for 14.318 MHz reference clock outputs
Input 14.318 MHz crystal input
2
3
X2
Output 14.318 MHz crystal output
4
PCICLK_F
PCICLK (1:5)
GNDPCI
VDDPCI
VDD48
Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Output 3.3 V PCI clock outputs, generating timing requirements for Pentium IIä
Power Ground for PCI clock outputs
Power 3.3 V power for the PCI clock outputs
Power 3.3 V power for 48/24 MHz clocks
5,6,9,10,11
7
8
12
13
48 MHz
Output 3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for
testing, active high = normal operation
Power Ground for 48/24 MHz clocks
14
15
TS#/48/24MHz
GND48
Output
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
16
SEL 100/66#
Input
selected cases.
Asynchronous active low input pin used to power down the device into a low power
17
18
PD#
Input
Input
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
CPU_STOP#
19
20
VDD
Power Isolated 3.3 V power for core
Synchronous active low input used to stop the PCICLK in active low state. It will not
PCI-Stop#
Input
effect PCICLK_F or any other outputs.
21
22
23,24
25
GND
GNDL
CPUCLK(1:0)
VDDL
Power Isolated ground for core
Power Ground for CPU clock outputs
Output 2.5 V CPU clock outputs
Power 2.5 V power for CPU clock outputs
3.3 V 14.318 MHz reference clock output and power-on spread spectrum enable
26
REF1/SPREAD# Output option. Active low = spread spectrum clocking enable. Active high = spread
spectrum clocking disable.
3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
27
28
REF0/SEL48#
VDDREF
Output
Power 3.3 V power for 14.318 MHz reference clock outputs.
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2
ICS9248-50
SelectFunctions
Functionality
PCI,
PCI_F
CPUCLK
REF0
Tristate
HI - Z
HI - Z
HI - Z
Testmode
TCLK/21
TCLK/61
TCLK1
SEL
100/66#
TS#
Function
0
0
0
0
1
1
1
1
0
-
Tri-State
(Reserved)
(Reserved)
-
1
0
-
Active 66.6MHz CPU, 33.3 PCI
Test Mode
(Reserved)
-
(Reserved)
1
Active 100MHz CPU, 33.3 PCI
Power Management
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
Low
PCICLK PCICLK_F
REF
Crystal
Off
VCOs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Stopped
Low
33.3MHz
33.3MHz
33.3MHz
33.3MHz
Running Running Running
Running Running Running
Running Running Running
Running Running Running
Low
33.3 MHz
Low
100/66.6MHz
100/66.6MHz 33.3 MHz
ICS9248-50PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free
running PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
1
1
1
PCI_STOP#
PD#
0 (Disabled)2
1 (Enabled)1
1
1 (Normal Operation)3
0 (Power Down)4
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
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3
ICS9248-50
CPU_STOP#Timing Diagram
ICS9248-50
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9248-50.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP#Timing Diagram
ICS9248-50
ICS9248-50
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
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4
ICS9248-50
PD#Timing Diagram
ICS9248-50
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
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ICS9248-50
Absolute Maximum Ratings
DD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . 0°C to +115°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIL
VSS - 0.3
V
IIH
VIN = VDD
0.1
2.0
-100
60
5
mA
mA
mA
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
180
180
72
Operating
Supply Current
66
16
23
100
Power Down
Supply Current
Input frequency
Input Capacitance1
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
70
600
mA
Fi
VDD = 3.3 V;
11
27
14.318
16
5
MHz
pF
CIN
Logic Inputs
CINX
Ttrans
TSTAB
X1 & X2 pins
36
3
45
3
pF
Transition Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ns
3
TCPU-PCI VT = 1.5 V; VTL = 1.25 V
1.5
4
0278I—06/03/03
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ICS9248-50
Electrical Characteristics - CPUCLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
IOH = -12.0 mA
MIN
1.8
TYP
2.3
MAX UNITS
V
IOL = 12 mA
0.31
0.4
-27
V
mA
mA
ns
ns
%
VOH = 1.7 V
IOL2B
VOL = 0.7 V
27
0.4
0.4
44
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.15
1.4
48
1.6
1.6
1
Fall Time
tf2B
1
Duty Cycle
dt2B
55
1
Skew
tsk2B
VT = 1.25 V
134
10
175
10.5
200
+250
ps
ns
ps
ps
Jitter
period(norm) VT = 1.25 V; 100MHz
10
1
Jitter
tjcyc-cyc2B VT = 1.25 V
186
150
1
tjabs2B
VT = 1.25 V
Jitter, Absolute
-250
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF/48MHz/24MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
3.1
MAX UNITS
V
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.17
-44
0.4
-22
V
mA
mA
ns
ns
%
IOH5
IOL5
16
45
42
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.4
1.1
53
4
Fall Time1
Duty Cycle1
4
dt5
tj1s5
tjabs5
tj1s5
tjabs5
VT = 1.5 V
55
VT = 1.5 V, REF
VT = 1.5 V, REF
VT = 1.5 V, 48 MHz
VT = 1.5 V, 48 MHz
185
385
169
469
250
800
250
800
ps
ps
ps
ps
Jitter1
Jitter1
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7
ICS9248-50
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN
2.1
TYP
3.3
MAX UNITS
V
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.1
0.4
-22
57
V
mA
mA
ns
ns
%
16
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.8
50
2
Fall Time1
Duty Cycle1
tf1
2
dt1
55
Skew1
tsk1
tjcyc-cyc
tj1s
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
222
186
52
500
500
150
500
ps
ps
ps
ps
Jitter1
tjabs
200
1Guaranteed by design, not 100% tested in production.
0278I—06/03/03
8
ICS9248-50
GeneralLayoutPrecautions:
Notes:
CapacitorValues:
0278I—06/03/03
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ICS9248-50
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
2.00
-
MIN
-
MAX
.079
-
A
A1
A2
b
0.05
1.65
0.22
0.09
.002
.065
.009
.0035
1.85
0.38
0.25
.073
.015
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
7.40
5.00
8.20
5.60
.291
.197
.323
.220
E1
e
0.65 BASIC
0.0256 BASIC
L
0.55
0.95
.022
.037
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
3.30
6.50
6.50
7.50
7.50
8.50
8.50
10.50
10.50
12.90
8
2.70
5.90
5.90
6.90
6.90
7.90
7.90
9.90
9.90
12.30
.106
.232
.232
.271
.271
.311
.311
.390
.390
.484
.130
.256
.256
.295
.295
.335
.335
.413
.413
14
16
18
20
22
24
28
30
38
.508
6/1/00 Rev B
MO-150 JEDEC
Doc.# 10-0033
Ordering Information
9248yF-50-T
XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
0278I—06/03/03
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