ICS9248YF-87 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9248YF-87 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总13页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-87
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Pin Configuration
Output Features:
•
•
•
•
•
•
•
•
2- CPUs @2.5V, up to 155MHz.
9 - SDRAM @ 3.3V, up to 155MHz.
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V
2- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V
1- REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 155MHz frequency support
Support FS0-FS3 strapping status bit for I2C read back.
Support power management: Power down Mode from I2C
programming.
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
Skew Specifications:
48-Pin 300mil SSOP
*: These inputs have a 120K pull up to VDD.
1: These are double strength.
•
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
For group skew specification, please refer to group
timing relationships table.
Block Diagram
Functionality
PCICLK IOAPIC
PLL2
48MHz
IOAPIC
(PCI)
(MHz)
2
CPU
CPU/
SDRAM 3V66
(3V66*
1/2)
(PCI*
1/2)
FS3 FS2 FS1 FS0
24_48MHz
(MHz) SDRAM (MHz)
(MHz)
/ 2
(MHz)
(MHz)
X1
X2
XTAL
OSC
83.3
1.00
83.3
55.48
82.67
27.74
41.33
51.67
36.00
35.00
37.33
50.00
35.00
34.17
35.67
46.00
34.34
33.40
33.40
44.53
33.40
13.87
20.67
25.83
18.00
17.50
18.67
25.00
17.50
17.08
17.83
23.00
17.17
16.70
16.70
22.27
16.70
27.74
41.33
51.67
36.00
35.00
37.33
50.00
35.00
34.17
35.67
46.00
34.34
33.40
33.40
44.53
33.40
REF1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
124.00
155.00
143.96
70.00
1.00 124.00
1.00 155.00 103.33
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK [1:0]
2
8
1.33 108.00
0.67 105.00
1.00 112.00
72.00
70.00
74.67
SDRAM
DIVDER
112.00
150.00
140.00
68.33
SDRAM [7:0]
SDRAM_F
1.00 150.00 100.00
SEL24_48#
SDATA
1.33 105.00
0.67 102.50
1.00 107.00
1.00 138.00
1.33 103.00
0.67 100.20
1.00 100.30
1.00 133.60
1.33 100.20
70.00
68.33
71.33
92.00
68.67
66.80
66.80
89.07
66.80
Control
Logic
I2C
{
IOAPIC
DIVDER
SCLK
IOAPIC
107.00
138.00
137.33
66.80
FS[3:0]
PCI
DIVDER
PD#
PCICLK [7:0]
8
2
Config.
Reg.
100.30
133.60
133.60
3V66
DIVDER
3V66 [1:0]
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248-87 Rev D 10/27/00
Third party brands and names are the property of their respective owners.
ICS9248-87
Preliminary Product Preview
General Description
Power Groups
GNDREF, VDDREF=REF1, X1, X2
GNDPCI, VDDPCI=PCICLK[7:0]
GNDSDRAM, VDDSDRAM = SDRAM [8:0]
GND3V66,VDD3V66=3V66
The ICS9248-87 is the single chip clock solution for designs
using 810/810E style chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-87
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
VDD48 = 48MHz, 24MHz
GNDCOR, VDDCOR = supply for PLL core
VDDLAPIC = IOAPIC
GNDLCPU, VDDLCPU=CPUCLKL[1:0]
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
REF1
TYPE
OUT
IN
DESCRIPTION
14.318 MHz reference clock.
1
FS3
Frequency select pin.
2, 6, 16, 24, 27, 34,
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
VDD
PWR
42
3
X1
X2
IN
Crystal input,nominally 14.318MHz.
4
OUT
Crystal output, nominally 14.318MHz.
5, 9, 13, 20, 26, 30,
GND
PWR
Ground pin for 3V outputs.
38
8, 7
3V66 [1:0]
FS0
OUT
IN
3V66 clock outputs.
Frequency select pin.
10
11
12
PCICLK0
FS1
OUT
IN
PCI clock output.
Frequency select pin.
PCICLK1
FS2
OUT
IN
PCI clock output.
Frequency select pin.
PCICLK2
PCICLK [7:3]
48MHz
OUT
OUT
OUT
PCI clock output.
19, 18, 17, 15, 14
21, 22
PCI clock outputs.
48MHz output clocks
Sel pin for enabling 24MHz or 48MHz
H=24MHz L=48MHz
SEL24_48#
IN
23
24_48MHz
SDATA
SCLK
OUT
IN
Clock output for super I/O/USB
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
25
28
IN
29
PD#
IN
SDRAM clock output - free running not affected by I2C
31
SDRAM_F
OUT
OUT
32, 33, 35, 36, 37,
SDRAM [7:0]
SDRAM clock outputs
39, 40, 41
43
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
PWR
OUT
PWR
OUT
PWR
Ground pin for the CPU clocks.
CPU clock outputs.
44, 45
46
Power pin for the CPUCLKs. 2.5V
2.5V clock output
47
48
VDDLAPIC
Power pin for the IOAPIC. 2.5V
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2
ICS9248-87
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
3
ICS9248-87
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
IOAPIC
(MHz)
=PCI/2 =PCI
CPUCLK
(MHz) SDRAM
CPU/
SDRAM
(MHz)
3V66 PCICLK
Bit (2, 7:4)
(MHz)
(MHz)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
83.3
124.00
155.00
143.96
70.00
112.00
150.00
140.00
68.33
107.00
138.00
137.33
66.80
100.30
133.60
133.60
145.00
140.00
136.00
130.00
129.00
127.00
121.00
119.00
117.00
114.00
110.00
105.00
75.33
1.00
1.00
1.00
1.33
0.67
1.00
1.00
1.33
0.67
1.00
1.00
1.33
0.67
1.00
1.00
1.33
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.67
1.33
1.33
1.33
83.3
55.48
82.67
103.33
72.00
70.00
74.67
100.00
70.00
68.33
71.33
92.00
68.67
66.80
66.80
89.07
66.80
96.67
93.33
90.67
86.67
86.00
84.67
80.67
79.33
78.00
76.00
73.33
70.00
75.33
76.67
75.33
73.33
27.74 13.87 27.74
41.33 20.67 41.33
51.67 25.83 51.67
36.00 18.00 36.00
35.00 17.50 35.00
37.33 18.67 37.33
50.00 25.00 50.00
35.00 17.50 35.00
34.17 17.08 34.17
35.67 17.83 35.67
46.00 23.00 46.00
34.34 17.17 34.34
33.40 16.70 33.40
33.40 16.70 33.40
44.53 22.27 44.53
33.40 16.70 33.40
48.33 24.17 48.33
46.67 23.33 46.67
45.33 22.67 45.33
43.33 21.67 43.33
43.00 21.50 43.00
42.33 21.17 42.33
40.33 20.17 40.33
39.67 19.83 39.67
39.00 19.50 39.00
38.00 19.00 38.00
36.67 18.33 36.67
35.00 17.50 35.00
37.67 18.83 37.67
38.33 19.17 38.33
37.67 18.83 37.67
36.67 18.33 36.67
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
124.00
155.00
108.00
105.00
112.00
150.00
105.00
102.50
107.00
138.00
103.00
100.20
100.30
133.60
100.20
145.00
140.00
136.00
130.00
129.00
127.00
121.00
119.00
117.00
114.00
110.00
105.00
113.00
115.00
113.00
110.00
00100
Note1
Bit 2,
Bit 7:4
153.33
150.63
146.63
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
1- Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
1) All entries selectable through I2C. Entries 1 -16 are also selectable through FS pins.
2) The IOAPIC Frequency change from IOAPIC=PCICLK/2 to IOAPIC=PCICLK is
controlled by IOAPC_Freq control in I2C Byte 3 Bit 1, default is IOAPIC=PCICLK/2.
3) Read back code of PWD shows revision ID.
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
4
ICS9248-87
Preliminary Product Preview
Byte 0: Control Register Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
SDRAM7
BIT PIN# PWD
DESCRIPTION
Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
32
33
35
36
37
39
40
41
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
-
-
0
0
0
0
0
1
1
0
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Reserved
Reserved
Reserved
Reserved
24/48MHz
48MHz
-
-
-
23
Bit1 21,22
Bit0
-
Reserved
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
-
-
-
-
-
-
0
X
X
X
1
Reserved
FS2#
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
19
18
17
15
14
12
11
10
1
1
1
1
1
1
1
1
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
FS1#
FS0#
IOAPIC
(SEL24_48#)#
FREQ_IOAPIC
=1=>IOAPIC=PCICLK/2
FREQ_IOAPIC=0=>
IOAPIC= PCICLK
X
Bit1
Bit0
-
-
1
X
FS3#
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Notes:
Note: Dont write into this register, writing into this
register can cause malfunction
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
3. SDRAM_F is free running and cannot be turned off by I2C
Third party brands and names are the property of their respective owners.
5
ICS9248-87
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
The I/O pins designated by (input/output) on the ICS9248-
87 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
Third party brands and names are the property of their respective owners.
6
ICS9248-87
Preliminary Product Preview
Fig. 2a
Fig. 2b
Third party brands and names are the property of their respective owners.
7
ICS9248-87
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-87 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
8
ICS9248-87
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
CPU 100MHz
Offset Tolerance
5.0ns 500ps
CPU 133MHz
Offset Tolerance
0.0ns 500ps
Offset
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
2.5ns
7.5ns
0.0ns
500ps
5.0ns
0.0ns
500ps
500ps
0.0ns
0.0ns
500ps
500ps
SDRAM to 3V66
500ps
3V66 to PCI
PCI to PCI
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
USB & DOT
Asynch
Asynch
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
-5
2.0
-100
60
IIL2
-200
IDD3.3OP
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
VDD = 3.3 V;
400
Supply Current
Input frequency
Pin Inductance
Fi
14.318
MHz
nH
pF
Lpin
CIN
7
5
Logic Inputs
Input Capacitance1
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
t
PZH,tPZH output enable delay (all outputs)
1
1
10
10
tPLZ,tPZH
output disable delay (all outputs)
nS
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-87
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
50
1
Skew
tsk2B
VT = 1.25 V
175
250
ps
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
175
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9248-87
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
9
9
2
30
30
Ω
Ω
1
RDSN4B
VOH4\B
VOL4B
IOH4B
V
0.4
-27
30
V
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
IOL4B
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
1
Duty Cycle
dt4B
Jitter
tjcyc-cyc
VT = 1.25 V
500
250
ps
ps
1
Tsk4
Skew
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
Jitter
tjcyc-cyc VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9248-87
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
500
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
60
Ω
Ω
1
RDSN5
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
nS
nS
%
1
tr5
1.8
1.7
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
45
55
1
Jitter
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
VT = 1.5 V
500
1000
250
pS
pS
pS
1
tjcyc-cyc
Skew
Tsk
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9248-87
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.620
MAX
.630
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9248yF-87
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS,AV=StandardDevice
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Third party brands and names are the property of their respective owners.
13
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Processor Specific Clock Generator, 133.37MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, TSSOP-48
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