ICS9250-25 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9250-25 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总14页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9250-25
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E and Solano type chipset
VDDREF
X1
1
2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4*1
VDDLAPIC
IOAPIC
X2
3
4
5
6
7
8
9
Output Features:
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
•
•
•
•
•
•
•
2 - CPUs @ 2.5V, up to 153.33MHz.
13 - SDRAM @ 3.3V, up to 153.33MHz.
3 - 3V66 @ 3.3V, 2x PCI MHz.
8 - PCI @3.3V.
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
VDD3V66
VDDPCI
1*FS0/PCICLK0
1*FS1/PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PD#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1 - REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 153.33MHz frequency support
Support power management through PD#.
Spread spectrum for EMI control (± 0.25%)
center spread.
24MHz/FS2*
48MHz/FS3*1
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
•
•
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
•
•
CPU Output Jitter: <250ps
IOAPIC Output Jitter: <500ps
56-Pin 300 mil SSOP
1ꢀ These pins will have 1ꢀ5 to 2X drive strengthꢀ
* 120K ohm pull-up to VDD on indicated inputsꢀ
•
•
•
•
•
•
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
Block Diagram
3V66 Output Skew <175ps
For group skew timing, please refer to the
Group Timing Relationship Table.
PLL2
48MHz
24MHz
/ 2
X1
X2
XTAL
OSC
REF0
PLL1
Spread
CPU
DIVDER
CPUCLK [1:0]
2
Spectrum
SDRAM
DIVDER
SDRAM [11:0]
SDRAM_F
IOAPIC
12
Control
Logic
FS[4:0]
PD#
IOAPIC
DIVDER
Config.
Reg.
PCI
DIVDER
PCICLK [7:0]
3V66 [2:0]
SDATA
SCLK
8
3
3V66
DIVDER
PRODUCT PREVIEW documents contain information on new products
in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.
9250-25 Rev A 10/03/00
Third party brands and names are the property of their respective owners.
ICS9250-25
Preliminary Product Preview
General Description
The ICS9250-25 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipsetꢀ It provides all
necessary clock signals for such a systemꢀ
Spread spectrum may be enabled through I2C programmingꢀ Spread spectrum typically reduces system EMI by 8dB to 10dBꢀ This
simplifies EMI qualification without resorting to board design iterations or costly shieldingꢀ The ICS9250-25 employs a proprietary
closed loop design, which tightly controls the percentage of spreading over process and temperature variationsꢀ
Serial programming I2C interface allows changing functions, stop clock programming and frequency selectionꢀ
Pin Configuration
PIN
PIN NAME
VDD
TYPE
DESCRIPTION
NUMBER
1, 9, 10, 18, 25,
32, 33, 37, 45
PWR 3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
2
3
X1
X2
IN
OUT
4, 5, 14, 21,
28, 29, 36,
41, 49
GND
PWR Ground pins for 3.3V supply
8, 7, 6
3V66 [2:0]
OUT 3.3V Fixed 66MHz clock outputs for HUB
PCICLK01
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
11
FS0
PCICLK11
IN
IN
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock outputs, with Synchronous CPUCLKS
12
FS1
IN
Logic input frequency select bit. Input latched at power on.
20, 19, 17, 16,
15, 13
PCICLK [7:2]
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
22
PD#
IN
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
23
24
SCLK
SDATA
48MHz
FS3
IN
IN
Clock input of I2C input
Data input for I2C serial input.
OUT 3.3V Fixed 48MHz clock output for USB
34
35
IN
IN
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
FS2
24MHz
SDRAM_F
OUT 3.3V fixed 24MHz output
OUT 3.3V free running 100MHz SDRAM not affected by I2C
38
48, 47, 44, 43,
42, 40, 39, 31, SDRAM [11:0]
30, 30, 27, 26
3.3V output running 100MHz. All SDRAM outputs can be turned off
OUT
through I2C
50
GNDL
PWR Ground for 2.5V power supply for CPU & APIC
51, 52
CPUCLK [1:0]
OUT 2.5V Host bus clock output. Output frequency derived from FS pins.
53, 55
54
VDDL
IOAPIC
FS4
PWR 2.5V power suypply for CPU, IOAPIC
OUT 2.5V clock outputs running at 16.67MHz.
IN
Logic input frequency select bit. Input latched at power on.
56
REF01
OUT 3.3V, 14.318MHz reference clock output.
Third party brands and names are the property of their respective owners.
2
ICS9250-25
Preliminary Product Preview
Frequency Selection
CPU
MHz
SDRAM
MHz
PCI
FS4 FS3 FS2 FS1 FS0
3V66 MHz
IOAPIC MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
55.00
60.00
66.80
68.33
70.00
72.00
75.00
77.00
83.30
82.50
90.00
55.00
60.00
66.80
68.33
70.00
72.00
75.00
77.00
55.53
60.00
66.87
68.67
75.00
76.67
80.00
83.33
64.00
65.00
66.85
68.50
70.00
72.50
75.00
76.67
62.50
65.00
66.85
68.50
70.00
72.50
75.00
76.67
27.5
30
33.4
34.165
35
13.75
15
16.7
17.0825
17.5
18
100.20
102.50
105.00
108.00
112.50
115.50
83.30
36
37.5
38.5
27.8
30.0
33.4
34.3
37.5
38.3
40.0
41.7
32.0
32.5
33.4
34.3
35.0
36.3
37.5
38.3
31.3
32.5
33.4
34.3
35.0
36.3
37.5
38.3
18.75
19.25
13.9
15.0
16.7
17.2
18.8
19.2
20.0
20.8
16.0
16.3
16.7
17.1
17.5
18.1
18.8
19.2
15.6
16.3
16.7
17.1
17.5
18.1
18.8
19.2
90.00
90.00
100.30
103.00
112.50
115.00
120.00
125.00
128.00
130.00
133.70
137.00
140.00
145.00
150.00
153.33
125.00
130.00
133.70
137.00
140.00
145.00
150.00
153.33
100.30
103.00
112.50
115.00
120.00
125.00
128.00
130.00
133.70
137.00
140.00
145.00
150.00
153.33
93.75
97.50
100.28
102.75
105.00
108.75
112.50
115.00
Clock Enable Configuration
REF,
PD#
CPUCLK
SDRAM
IOAPIC
66MHz
PCICLK
Osc
VCOs
48MHz
LOW
ON
0
1
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
Third party brands and names are the property of their respective owners.
3
ICS9250-25
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)
Bit
PWD
Description
CPUCLK
MHz
SDRAM
MHz
3V66
MHz
IOAPIC
MHz
Bit (2,7:4)
PCICLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
55.00
60.00
66.80
68.33
70.00
72.00
75.00
77.00
83.30
82.50
90.00
55.00
60.00
66.80
68.33
70.00
72.00
75.00
77.00
55.53
60.00
66.87
68.67
75.00
76.67
80.00
83.33
64.00
65.00
66.85
68.50
70.00
72.50
75.00
76.67
62.50
65.00
66.85
68.50
70.00
72.50
75.00
76.67
27.5
30
33.4
34.165
35
13.75
15
16.7
17.0825
17.5
18
100.20
102.50
105.00
108.00
112.50
115.50
83.30
36
37.5
38.5
27.8
30.0
33.4
34.3
37.5
38.3
40.0
41.7
32.0
32.5
33.4
34.3
35.0
36.3
37.5
38.3
31.3
32.5
33.4
34.3
35.0
36.3
37.5
38.3
18.75
19.25
13.9
15.0
16.7
17.2
18.8
19.2
20.0
20.8
16.0
16.3
16.7
17.1
17.5
18.1
18.8
19.2
15.6
16.3
16.7
17.1
17.5
18.1
18.8
19.2
90.00
90.00
100.30
103.00
112.50
115.00
120.00
125.00
128.00
130.00
133.70
137.00
140.00
145.00
150.00
153.33
125.00
130.00
133.70
137.00
140.00
145.00
150.00
153.33
100.30
103.00
112.50
115.00
120.00
125.00
128.00
130.00
133.70
137.00
140.00
145.00
150.00
153.33
93.75
00001
Note 1
Bit
(2, 7:4)
97.50
100.28
102.75
105.00
108.75
112.50
115.00
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,6:4
0- Normal
Bit 3
Bit 1
Bit 0
0
1
0
1- Spread spectrum enable ± 0.25% Center Spread
0- Running
1- Tristate all outputs
Notes:
1ꢀ Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3ꢀ
2ꢀ The I2C readback for Bit 2, 7:4 indicate the revision codeꢀ
Third party brands and names are the property of their respective owners.
4
ICS9250-25
Preliminary Product Preview
Byte 2: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
FS3#
Bit
Pin# PWD
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
35
-
X
X
X
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
39
40
42
43
44
46
47
48
1
1
1
1
1
FS0#
FS2#
24MHz
(Reserved)
48MHz
1
34
-
1
1
1
1
1
(Reserved)
SDRAM_F
38
1
Byte 3: Control Register
(1 = enable, 0 = disable)
Byte 4: Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Bit
Pin# PWD
Description
3V66_2
3V66_0
3V66_1
FS4#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8
6
1
1
7
1
-
54
-
51
52
X
1
X
1
1
1
1
1
Byte 5: Control Register
(1 = enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Bit
Pin# PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Bit
Pin# PWD
Description
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
-
-
26
27
30
31
Note: Dont write into this register, writing into this register
can cause malfunction
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled from switchingꢀ These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operationꢀ
2ꢀ PWD = Power on Default
Third party brands and names are the property of their respective owners.
5
ICS9250-25
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 4ꢀ6 V
I/O Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 3ꢀ6V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Case Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods may affect product
reliabilityꢀ
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
2.5ns
7.5ns
0.0ns
Tolerance
500ps
Offset
5.0ns
5.0ns
0.0ns
Tolerance
500ps
Offset
0.0ns
0.0ns
0.0ns
Tolerance
500ps
Offset
3.75ns
0.0ns
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
500ps
500ps
500ps
500ps
SDRAM to 3V66
500ps
500ps
500ps
3.75ns
500ps
3V66 to PCI
PCI to PCI
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5 -3.5ns
0.0ns
500ps
1.0ns
N/A
USB & DOT
Asynch
Asynch
Asynch
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
-5
A
µ
IIL2
-200
IDD3.3OP
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
Supply Current
Input frequency
Pin Inductance
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
Lpin
CIN
7
5
Input Capacitance1
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
tPZH,tPZH output enable delay (all outputs)
tPLZ,tPZH
1
1
10
10
output disable delay (all outputs)
nS
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9250-25
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
ns
ps
ps
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
50
1
Skew
tsk2B
VT = 1.25 V
175
250
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.4
0.4
45
1
tr1
1.6
1.6
55
1
Fall Time
tf1
1
Duty Cycle
dt1
1
Skew
tsk1
VT = 1.5 V
175
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9250-25
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
9
9
2
30
30
Ω
Ω
1
RDSN4B
VOH4\B
VOL4B
IOH4B
V
0.4
-21
31
V
VOH@ min = 1.4 V, VOH@ MAX = 2.5 V
VOL@ MIN = 1.0 V, VOL@ MAX= 0.2
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-36
36
mA
mA
nS
nS
%
IOL4B
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
1
Duty Cycle
dt4B
Jitter
tjcyc-cyc
VT = 1.25 V
500
pS
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
Jitter
tjcyc-cyc VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9250-25
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
500
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 48M, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP
MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
60
Ω
Ω
1
RDSN5
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
nS
nS
%
1
tr5
1.8
1.7
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
45
55
1
Jitter
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
500
1000
pS
pS
1
tjcyc-cyc
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9250-25
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
Controller (host) sends the read address D3(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for verificationꢀ
Read-Back will support Intel PIIX4 "Block-Read" protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those two bytesꢀ The
data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
Third party brands and names are the property of their respective owners.
10
ICS9250-25
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) on the ICS9250-25
serve as dual signal functions to the deviceꢀ During initial
power-up, they act as input pinsꢀThe logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latchꢀ At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output functionꢀ In this
modethepinsproducethespecifiedbufferedclockstoexternal
loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either theVDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9250-25
Preliminary Product Preview
Power Down Waveform
Note
1ꢀ After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiionꢀ
2ꢀ Power-up latency <3msꢀ
3ꢀ Waveform shown for 100MHz
Third party brands and names are the property of their respective owners.
12
ICS9250-25
Preliminary Product Preview
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
Third party brands and names are the property of their respective owners.
13
ICS9250-25
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
E1
e
10.033
7.391
10.668
7.595
.395
.291
.420
.299
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.720
MAX
.730
56
18.288
18.542
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9250yF-25-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new products
in the sampling or preproduction phase of development. Characteristic
data and other specifications are subject to change without notice.
Third party brands and names are the property of their respective owners.
14
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