ICS9250YF-12-T [ICSI]
Frequency Timing Generator for PENTIUM II/III Systems; 频率时序发生器奔腾II / III系统
| 型号： | ICS9250YF-12-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for PENTIUM II/III Systems |
| 文件： | 总12页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-12
Frequency Timing Generator for PENTIUM II/III Systems
General Description
Features
Generates the following system clocks:
The ICS9250-12 is a main clock synthesizer chip for
Pentium II based systems using Rambus Interface DRAMs.
This chip provides all the clocks required for such a system
when used with a Direct Rambus Clock Generator (DRCG)
chip such as the ICS9212-01, 02, 03 and a PCI buffer 9112-17.
- 4CPUclocks(2.5V,100/133MHz)
- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)
- 2CPU/2clocks(2.5V, 50/66MHz)
-3IOAPICclocks(2.5V,16.67MHz)
-4Fixedfrequency66MHzclocks(3.3V, 66MHz)
-2REFclocks(3.3V,14.318MHz)
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI
by 8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9250-12 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.
-1USBclock(3.3V,48MHz)
Efficient power management through PD#, CPU_STOP#
andPCI_STOP#.
0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
The CPU/2 clocks are inputs to the DRCG.
Usesexternal14.318MHzcrystal.
Key Specification:
CPU Output Jitter: 150ps
IOAPIC Output Jitter: 250ps
CPU/2, 3V66, PCIOutputJitter:250ps
CPU(0:3)CPU/2OutputSkew:<175ps
PCI_F, PCI1:7OutputSkew:<500ps
3V66(0:3)OutputSkew<250ps
Pin Configuration
IOAPIC(0:2)OutputSkew<250ps
CPU to 3V66 (0:3) Output Offset: 0.0 - 1.5ns (CPU leads)
CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)
CPU toAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Block Diagram
56-pin SSOP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-12 Rev B 2/23/00
information being relied upon by the customer is current and accurate.
ICS9250-12
Pin Descriptions
Pin number
Pin name
GNDREF
REF(0:1)
Type
PWR
Description
1
Gnd pin for REF clocks
2, 3
OUT
PWR
IN
14.318MHz reference clock outputs at 3.3V
Power pin for REF clocks
4
VDDREF
X1
5
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
6
X2
OUT
PWR
7, 13, 19
GNDPCI
Gnd pin for PCICLKs
Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected
by the PCI_STOP# input.
8
PCICLK_F
OUT
OUT
9, 11, 12, 14, 15,
17, 18
PCICLK[1:7]
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
10, 16
20, 24
VDDPCI
GND66
PWR
PWR
3.3Volts power pin for PCICLKs
Gnd pin for 3V66 outputs
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is
driven active..
21, 22, 25, 26
3V66[0:3]
OUT
23, 27
28
VDD66
PWR
IN
power pin for the 3V66 clocks.
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
SEL 133/100#
29
GND48
48MHz
VDD48
SEL[0:1]
PWR
OUT
PWR
IN
Ground pin for the 48MHz output
30
Fixed 48MHz clock output. 3.3V
31
Power pin for the 48MHz output.
32, 33
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU, PCI,
IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz
clocks. 0.5% down spread modulation.
34
35
SPREAD#
PD#
IN
IN
This asynchronous input powers down the chip when drive active(Low).
The internal PLLs are disabled and all the output clocks are held at a Low
state.
This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at
logic "0" when driven active(Low). Does not affect the CPU/2 clocks.
36
37
CPU_STOP#
PCI_STOP#
IN
IN
This asynchronous input halts the PCICLK[1:7] at logic"0" when driven
active(Low). PCICLK_F is not affected by this input.
38
GNDCOR
VDDCOR
VDDLCPU
GNDLCPU
PWR
PWR
PWR
PWR
Ground pin for the PLL core
39
Power pin for the PLL core. 3.3V
43, 47
40, 44
Power pin for the CPUCLKs. 2.5V
Ground pin for the CPUCLKs
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state
of the SEL 133/100MHz.
41, 42, 45, 46
48
CPUCLK[0:3]
GNDLCPU/2
CPU/2[0:1]
OUT
PWR
OUT
PWR
Ground pin for the CPU/2 clocks.
2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on
the state of the SEL 133/100# input pin.
49, 50
51
52
VDDLCPU/2
Power pin for the CPU/2 clocks. 2.5V
GNDLIOAPIC PWR
IOAPIC[0:2] OUT
VDDLIOAPIC PWR
Ground pin for the IOAPIC outputs.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at
16.67MHz.
53, 54, 55
56
Power pin for the IOAPIC outputs. 2.5V.
2
ICS9250-12
Frequency Select:
SEL
CPU
MHz
CPU/2
MHz
3V66
MHz
PCI
MHz
48
MHz
REF IOAPIC
133/100- SEL1 SEL0
#
Comments
MHz
MHz
0
0
0
0
0
1
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Hi-Z
N/A
Tri-state
Reserved
48MHz PLL
disabled
0
0
1
1
1
0
0
1
0
100
100
50
50
66
66
33
33
Hi-Z 14.318
16.67
16.67
48
TCLK/-
2
14.318
TCLK/2 TCLK/4 TCLK/4 TCLK/8
TCLK TCLK/16 Test mode (1)
1
1
1
0
1
1
1
0
1
N/A
133
133
N/A
66
66
N/A
66
66
N/A
33
33
N/A
Hi-Z 14.318
48 14.318
N/A
N/A
16.67
16.67
Reserved
Note:
1. TCLK is a test clock driven on the x1 input during test mode.
ICS9250-12 Power Management Features:
REF.
48MHz
CPU_STOP#
PD# PCI_STOP# CPUCLK CPU/2 IOAPIC 3V66
PCI
LOW
LOW
ON
PCI_F
Osc
VCOs
OFF
ON
X
0
0
1
1
0
1
1
1
1
X
0
1
0
1
LOW
LOW
LOW
ON
LOW
ON
LOW
ON
LOW
LOW
LOW
ON
LOW
ON
LOW
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
LOW
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
4.All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.
5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions
except PD# = LOW
Power Groups:
VDDREF,GNDREF=REF,X1,X2
GNDPCI,VDDPCI=PCICLK
VDD66,GND66=3V66
VDD48,GND48=48MHz
VDDCOR,GNDCOR=PLLCore
VDDLCPU/2,GNDLCPU/2=CPU/2
VDDLIOAPIC,GNDIOAPIC=IOAPIC
3
ICS9250-12
Power Management Requirements:
Latency
Singal
Singal State
No. of rising edges of
PCICLK
0 (disabled)
1
1
CPU_STOP
PCI_STOP#
PD#
1 (enabled)
0 (disabled)
1
1 (enabled)
1
1 (normal operation)
0 (power down)
3mS
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
CPU_STOP# Timing Diagram
CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power
operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI
clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run
while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse. ONLYone rising edge of PCICLK_Fis allowed after the clock control logic
switched for both the CPU and 3V66 outputs to become enabled/disabled.
Notes:
1.All timing is referenced to the internal CPUCLK.
2. The internal label means inside the chip and is a reference only. This
in fact may not be the way that the control is designed.
3. CPU_STOP# signal is an input singal that must be made synchronous
to free running PCICLK_F
4. 3V66 clocks also stop/start before
5. PD# and PCI_STOP# are shown in a high state.
6. Diagramsshownwithrespectto133MHz. SimilaroperationwhenCPU
is100MHz
4
ICS9250-12
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used
to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a
full high pulse width is guaranteed. ONLYone rising edge of PCICLK_Fisallowed after the clock control logic switched for the
PCI outputs to become enabled/disabled.
Notes:
1. All timing is referenced to CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output.
3. Internal means inside the chip.
4. All other clocks continue to run undisturbed.
5. PD# and CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
5
ICS9250-12
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP#
are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9250 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
6
ICS9250-12
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
VIL
VSS-0.3
0.8
5
V
µA
µA
µA
IIH
VIN = VDD
0.1
2.0
-100
68
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP100 Select @ 100MHz; Max discrete cap loads
IDD3.3OP133 Select @ 133MHz; Max discrete cap loads
180
200
mA
uA
Supply Current
Power Down
Supply Current
Input frequency
Input Capacitance1
80
IDD3.3PD
CL = 0 pF; PWRDWN# = 0
62
Fi
VDD = 3.3 V
12
27
14.318
16
5
MHz
pF
CIN
Logic Inputs
CINX
TTrans
TS
X1 & X2 pins
36
1
45
3
pF
Transition Time1
Settling Time1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
Clk Stabilization1
TStab
3
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP100 Select @ 100MHz; Max discrete cap loads
IDD2.5OP133
CONDITIONS
MIN
TYP
19
MAX UNITS
25
mA
40
Supply Current
Select @ 133MHz; Max discrete cap loads
22
1Guaranteed by design, not 100% tested in production.
7
ICS9250-12
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
2.2
0.3
-35
27
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOH2B
IOL2B
19
0.4
0.4
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.2
1.25
48
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
55
%
1
Skew
tsk2B
VT = 1.25 V
80
175
+150
150
ps
1
Jitter, Absolute
Jitter, Cycle-to-cycle
tjabs2B
VT = 1.25 V
-150
61
ps
1
tjcyc-cyc2B
VT = 1.25 V
100
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
2.3
0.3
-35
27
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOH2B
IOL2B
19
0.4
0.4
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.1
1
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
48
55
%
1
Skew
tsk2B
VT = 1.25 V
80
175
+250
150
ps
1
Jitter, Absolute
Jitter, Cycle-to-cycle
tjabs2B
VT = 1.25 V
VT = 1.25 V
-250
70
ps
1
tjcyc-cyc2B
100
ps
1Guaranteed by design, not 100% tested in production.
8
ICS9250-12
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.25
-60
44
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
25
0.5
0.5
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.3
48
2
2
ns
ns
%
ps
dt1
tsk1
55
250
VT = 1.5 V
120
Jitter, Absolute1
tjabs1
VT = 1.5 V
VT = 1.5 V
-250
100
150
250
500
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc1
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
0.2
-60
45
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
25
0.5
0.5
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.7
1.6
50
2
2
ns
ns
%
ps
Fall Time1
Duty Cycle1
Skew1
dt1
tsk1
55
500
VT = 1.5 V
360
Jitter, Absolute1
tjabs1
VT = 1.5 V
VT = 1.5 V
-250
80
250
500
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc1
155
1Guaranteed by design, not 100% tested in production.
9
ICS9250-12
Electrical Characteristics - 48MHz, REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
2.9
0.3
-35
23
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
17
Rise Time1
Fall Time1
Duty Cycle1
Rise Time1
Fall Time1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V, 48MHz
VOH = 2.4 V, VOL = 0.4 V, 48MHz
VT = 1.5 V, 48MHz
2
4
4
ns
ns
%
2
dt5
tr5
tf5
45
1.5
1.5
45
50
2.2
1.9
55
4
VOL = 0.4 V, VOH = 2.4 V, REF
VOH = 2.4 V, VOL = 0.4 V, REF
ns
ns
4
Duty Cycle1
dt5
VT = 1.5 V, REF
VT = 1.5 V, 48MHz
VT = 1.5 V, REF
52
55
%
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle1
tjcyc-cyc5
tjcyc-cyc5
200
800
500
ps
ps
1000
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH4B
VOL4B
CONDITIONS
MIN
2
TYP
2.23
0.3
MAX UNITS
V
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-16
V
IOH4B
-36
22
mA
mA
IOL4B
19
0.4
0.4
45
Tr4B
Tf4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.25
49
1.6
1.6
55
ns
ns
%
ps
Fall Time1
Duty Cycle1
Dt4B
Skew1
tsk1B
VT = 1.25 V
120
250
Jitter, Absolute1
Tjabs4B
VT = 1.25 V
-250
130
87
250
500
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc4B VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
10
ICS9250-12
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of diagram.
2) 47 ohm / 56pf RC termination should be
used on all over 50MHz outputs.
3) Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3:100pFceramic
All unmarked capacitors are 0.01µF ceramic
ConnectionstoVDD:
11
ICS9250-12
Pin 1
.093
DIA. PIN (Optional)
D/2
Index
Area
E/2
PARTING LINE
H
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
-e-
B
A2
c
A
C
.004
SEE
DETAIL “A”
-E-
SEATING
PLANE
-D-
-C-
END VIEW
A1
SIDE VIEW
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.087
.008
.005
NOM.
.102
.012
.090
MAX.
.110
.016
.094
.0135
.010
MIN.
.720
NOM.
.725
MAX.
.730
A
A1
A2
B
AD
56
-
-
c
D
E
e
H
h
L
See Variations
.295
0.025 BSC
“For current dimensional specifications, see JEDEC 95.”
Dimensions in inches
.291
.299
.395
.010
.020
-
.420
.016
.040
.013
-
N
See Variations
0°
-
8°
56 Pin 300 mil SSOP Package
Ordering Information
ICS9250yF-12-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
12
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