ICS932S422C [ICSI]
PCIe Gen 2 main Clock for Intel-based Servers; 第二代PCIe主时钟为基于Intel的服务器
| 型号： | ICS932S422C |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PCIe Gen 2 main Clock for Intel-based Servers |
| 文件： | 总21页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS932S422C
Systems, Inc.
PCIe Gen 2 main Clock for Intel-based Servers
Recommended Application:
Features/Benefits:
PCIe Gen 2 & FBD compliant CK410B/CK410B+ clock for
Intel-based servers
•
Supports spread spectrum modulation, 0 to -0.5%
down spread
•
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
Output Features:
•
•
•
•
•
•
5 - 0.7V current-mode differential CPU pairs
4 - 0.7V current-mode differential SRC pair
4 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - 48MHz
•
•
•
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
Compliant with PCIe Gen II phase noise specifications
2 - REF, 14.318MHz
Key Specifications:
•
•
•
•
•
•
CPU cycle-cycle jitter: < 50ps
SRC cycle-cycle jitter: < 125ps
PCI cycle-cycle jitter: < 500ps
CPU output skew: < 100ps
SRC output skew: < 250ps
300ppm frequency accuracy on all outputs except
48MHz
•
100ppm frequency accuracy on 48MHz
Functionality
Pin Configuration
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
VDDPCI 1
GNDPCI 2
PCICLK0 3
PCICLK1 4
PCICLK2 5
PCICLK3 6
GNDPCI 7
VDDPCI 8
PCICLK_F0 9
PCICLK_F1 10
PCICLK_F2 11
VDD48 12
48MHz 13
GND48 14
VDDSRC 15
NC 16
56 FSLC/TEST_SEL
55 REF0
54 REF1
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 FSLA
47 VDDCPU
46 CPUCLKT0
45 CPUCLKC0
44 VDDCPU
43 CPUCLKT1
42 CPUCLKC1
41 GNDCPU
40 CPUCLKT2
39 CPUCLKC2
38 VDDCPU
37 CPUCLKT3
36 CPUCLKC3
35 VDDA
FSLC1 FSLB1 FSLA2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.67 100.00
133.33 100.00
200.00 100.00
166.67 100.00
333.33 100.00
100.00 100.00
400.00 100.00
33.33
33.33
33.33
33.33
33.33
33.33
33.33
Reserved
14.318
14.318
14.318
14.318
14.318
14.318
14.318
48.000
48.000
48.000
48.000
48.000
48.000
48.000
1. FSLB and FSLC are three-level inputs. Please see VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values. Also refer to the Test Clarification Table.
2.FSLA is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Vtt_PwrGd#/PD 17
SRCCLKC1 18
SRCCLKT1 19
GNDSRC 20
SRCCLKT2 21
SRCCLKC2 22
SRCCLKC3 23
SRCCLKT3 24
VDDSRC 25
SRCCLKT4 26
SRCCLKC4 27
VDDSRC 28
34 GNDA
33 IREF
32 CPUCLKT4
31 CPUCLKC4
30 SDATA
29 SCLK
56-pin SSOP & TSSOP
1412A—12/10/07
Integrated
Circuit
ICS932S422C
Systems, Inc.
Pin Description
Pin #
1
2
3
4
5
6
7
8
PIN NAME
PIN TYPE
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
OUT
PWR
PWR
N/A
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power pin for the 48MHz output.3.3V
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
9
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDD48
10
11
12
13
14
15
16
48MHz
GND48
VDDSRC
NC
48MHz clock output.
Ground pin for the 48MHz outputs
Supply for SRC clocks, 3.3V nominal
No Connection.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
17
Vtt_PwrGd#/PD
IN
18
19
20
21
22
23
24
25
26
27
28
SRCCLKC1
SRCCLKT1
GNDSRC
SRCCLKT2
SRCCLKC2
SRCCLKC3
SRCCLKT3
VDDSRC
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
Complement clock of differential push-pull SRC clock pair.
True clock of differential SRC clock pair.
Ground pin for the SRC outputs
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
SRCCLKT4
SRCCLKC4
VDDSRC
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
1412A—12/10/07
2
Integrated
Circuit
ICS932S422C
Systems, Inc.
Pin Description (Continued)
Pin #
29
30
PIN NAME
Type
IN
I/O
Pin Description
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
SCLK
SDATA
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard
value.
31
32
CPUCLKC4
CPUCLKT4
OUT
OUT
33
IREF
OUT
34
35
GNDA
VDDA
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
36
CPUCLKC3
OUT
37
38
39
CPUCLKT3
VDDCPU
OUT
PWR
OUT
CPUCLKC2
40
41
42
CPUCLKT2
GNDCPU
OUT
PWR
OUT
CPUCLKC1
43
44
45
CPUCLKT1
VDDCPU
OUT
PWR
OUT
CPUCLKC0
46
47
48
CPUCLKT0
VDDCPU
FSLA
OUT
PWR
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
49
FSLB/TEST_MODE
IN
50
51
52
53
54
55
GNDREF
X2
X1
VDDREF
REF1
REF0
PWR
OUT
IN
PWR
OUT
OUT
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
14.318 MHz reference clock.
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
56
FSLC/TEST_SEL
IN
1412A—12/10/07
3
Integrated
Circuit
ICS932S422C
Systems, Inc.
General Description
The ICS932S422C is a main clock synthesizer for CK410-generation Intel server platforms. The ICS932S422C is driven with
a 14.318MHz crystal. It generates 5 CPU output pairs up to 400MHz and PCI-Express clocks at 100 or 200 MHz. The 48 MHz
USB clock is an exact 48.000 MHz clock.
Block Diagram
REF(1:0)
X1
48MHz
XTAL
OSC.
FIXED PLL
CPU PLL
DIVIDER
X2
DIVIDERS
CPUCLK(4:0)
SRCCLK(3:0)
SRC/PCI
PLL
DIVIDERS
PCICLK(3:0), PCICLK_F(2:0)
FS(C:A)
TEST_SEL
CONTROL
LOGIC
TEST_MODE
VTT_PWRGD#/PD
SDATA
SCLK
IREF
Power Groups
Pin Number
Description
VDD
53
GND
50
Xtal, Ref
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL_48
1,8
15,25,28
35
2,7
20
34
12
14
47,44,38
41
CPUCLK clocks
1412A—12/10/07
4
Integrated
Circuit
ICS932S422C
Systems, Inc.
Single-ended Output Terminations
ICS932S422
Zo
Rs
CL=5pF
Test Load
SEPP Output Buffer
(Single Ended
Push Pull)
Zo
Zo
Rs
Rs
CL=5pF
CL=5pF
SEPP Output Buffer
(Single Ended
Push Pull)
The singled-ended outputs of the ICS 932S422 default to a drive strength of 2
loads. The REF clocks can be turned down to 1-load strength via the SMBus.
Suggested termination resistors are as follows for transmission lines with Zo =
50 ohms:
Single-ended outputs at 2-load strength (Power up default
for all single-ended outputs)
Driving 1 load, Rs = 33 ohms
Driving 2 loads, Rs = 7.5 ohms
Driving 1 load, Rs = 22 ohms
Single-ended outputs at 1-load strength (REF clock only)
1412A—12/10/07
5
Integrated
Circuit
ICS932S422C
Systems, Inc.
Absolute Maximum Rating
PARAMETER
SYMBOL
VDD_A
CONDITIONS
MIN
TYP
MAX
UNITS
V
Notes
-
1
3.3V Core Supply Voltage
VDD + 0.5V
3.3V Logic Input Supply
Voltage
Storage Temperature
-
1
VDD_In
GND - 0.5
VDD + 0.5V
V
Ts
-
-
-
-
-65
0
150
70
°C
°C
°C
V
1
1
1
1
Ambient Operating Temp
Case Temperature
Tambient
Tcase
115
Input ESD protection HBM
ESD prot
2000
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS*
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
Notes
VIH
VIL
IIH
2
VSS - 0.3
-5
V
V
1
1
1
5
uA
VIN = 0 V; Inputs with no pull-up
resistors
IIL1
IIL2
VIH_FS
-5
uA
uA
1
1
Input Low Current
VIN = 0 V; Inputs with pull-up resistors
-200
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
3.3 V +/-5%
3.3 V +/-5%
0.7
VDD + 0.3
0.35
V
V
1
1
VIL_FS
IDD3.3OP
IDD3.3OP
VSS - 0.3
Operating Supply Current
Operating Current
Full Active, CL = Full load;
all outputs driven
350
400
70
mA
mA
mA
mA
MHz
nH
1
1
1
1
2
1
1
1
1
all diff pairs driven
Powerdown Current
IDD3.3PD
all differential pairs tri-stated
VDD = 3.3 V
12
Input Frequency
Pin Inductance
Fi
14.31818
Lpin
7
5
6
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
pF
Input Capacitance
COUT
CINX
pF
pF
From VDD Power-Up or de-assertion
of PD to 1st clock
Clk Stabilization
Modulation Frequency
Tdrive_PD
TSTAB
1.8
33
ms
kHz
us
1
1
1
Triangular Modulation
30
CPU output enable after
PD de-assertion
PD fall time of
300
Tfall_PD
Trise_PD
5
ns
ns
V
1
1
1
1
PD rise time of
5
SMBus Voltage
VDD
VOL
2.7
4
5.5
0.4
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
@ IPULLUP
V
IPULLUP
mA
1
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
TRI2C
TFI2C
1000
300
ns
ns
1
1
Clock/Data Fall Time
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
1412A—12/10/07
6
Integrated
Circuit
ICS932S422C
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
NOTES
1
VO = Vx
Current Source Output Impedance
Zo
3000
Ω
Voltage High
Voltage Low
VHigh
VLow
Vovs
660
850
150
mV
mV
mV
mV
mV
mV
ppm
ns
1,3
1,3
1
Statistical measurement on single ended
signal
-150
Max Voltage
1150
Measurement on single ended signal
using absolute value.
Min Voltage
Vuds
Vx(abs)
d-Vx
-300
250
1
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
550
140
1
Variation of crossing over all edges
see Tperiod min-max values
400MHz nominal
1
ppm
-300
300
1,2
2
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
400MHz spread
ns
2
333.33MHz nominal
ns
2
333.33MHz spread
ns
2
266.66MHz nominal
3.7511
3.77
ns
2
266.66MHz spread
ns
2
200MHz nominal
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
ns
2
Average period
Tperiod
200MHz spread
ns
2
166.66MHz nominal
ns
2
166.66MHz spread
ns
2
133.33MHz nominal
ns
2
133.33MHz spread
ns
2
100.00MHz nominal
ns
2
100.00MHz spread
ns
2
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
ns
ns
Tabsmin
Absolute min period
ns
ns
ns
ns
tr
Rise Time
Fall Time
525
525
125
125
ps
tf
175
ps
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
ps
1
ps
1
dt3
tsk3
Duty Cycle
Skew
Measurement from differential wavefrom
CPU(4:0), VT = 50%
45
55
100
50
%
ps
ps
1
1
1
Measurement from differential wavefrom,
(CPU(4:0))
tjcyc-cyc
Jitter, Cycle to cycle
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
1412A—12/10/07
7
Integrated
Circuit
ICS932S422C
Systems, Inc.
Electrical Characteristics - SRC/SATA 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
1
V
O = Vx
Current Source Output Impedance
Zo
3000
Ω
Voltage High
Voltage Low
VHigh
VLow
Vovs
660
850
150
mV
mV
mV
mV
mV
mV
ppm
ns
1,3
1,3
1
Statistical measurement on single ended
signal
-150
Max Voltage
1150
Measurement on single ended signal
using absolute value.
Min Voltage
Vuds
Vx(abs)
d-Vx
-300
250
1
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
550
140
1
Variation of crossing over all edges
see Tperiod min-max values
100.00MHz nominal
1
ppm
-300
9.9970
9.9970
9.8720
175
300
1,2
2
10.0030
10.0533
Average period
Tperiod
100.00MHz spread
ns
2
Absolute min period
Rise Time
Tabsmin
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
ns
1,2
1
tr
525
525
125
125
ps
tf
Fall Time
175
ps
1
d-tr
d-tf
Rise Time Variation
Fall Time Variation
ps
1
ps
1
dt3
tsk3
Duty Cycle
Skew
Measurement from differential wavefrom
VT = 50%
45
55
%
ps
ps
1
1
1
250
125
tjcyc-cyc
Jitter, Cycle to cycle
Measurement from differential wavefrom
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
3IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
Electrical Characteristics - PCICLK/PCICLK_F
NOTES
PARAMETER
SYMBOL
CONDITIONS*
MIN
12
TYP
MAX
55
UNITS
Ω
RDSP
VO = VDD*(0.5)
Output Impedance
Output High Voltage
Output Low Voltage
1
1
1
1
1
1
1
1
1
1
1
1
VOH
VOL
IOH = -1 mA
IOL = 1 mA
2.4
V
0.55
-33
V
V OH @MIN = 1.0 V
-33
30
mA
mA
mA
mA
ns
IOH
Output High Current
Output Low Current
V
OH@MAX = 3.135 V
OL @ MIN = 1.95 V
V
IOL
V
OL @ MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
38
2
tr
tf
Rise Time
Fall Time
0.5
0.5
45
2
ns
dt1
Duty Cycle
55
250
500
%
tskew
tjcyc-cyc
VT = 1.5 V
Group Skew
Jitter, Cycle to cycle
ps
VT = 1.5 V
ps
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
3 Spread Spectrum is off
1412A—12/10/07
8
Integrated
Circuit
ICS932S422C
Systems, Inc.
Electrical Characteristics - USB48MHz
NOTES
PARAMETER
SYMBOL
CONDITIONS*
see Tperiod min-max values
48.00MHz output nominal
VO = VDD*(0.5)
MIN
-100
20.8313
12
TYP
MAX
100
UNITS
ppm
ns
Long Accuracy
ppm
1,2
2
Tperiod
RDSP
Clock period
20.8354
55
Output Impedance
Output High Voltage
Output Low Voltage
Ω
1
VOH
IOH = -1 mA
2.4
V
1
VOL
IOL = 1 mA
0.55
-33
V
1
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
mA
mA
ns
1
IOH
Output High Current
Output Low Current
1
1
IOL
27
2
1
tr_USB
tf_USB
dt1
Rise Time
Fall Time
1
1
1
2
ns
1
Duty Cycle
45
55
250
500
%
1
VT = 1.5 V
tskew
ps
Group Skew
Jitter, Cycle to cycle
1
tjcyc-cyc
VT = 1.5 V
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
MIN
-300
TYP
MAX
300
UNITS
ppm
ns
Notes
Long Accuracy
ppm
1,2
2
Tperiod
VOH
Clock period
69.8270
2.4
69.8550
Output High Voltage
Output Low Voltage
V
1
VOL
IOL = 1 mA
0.4
-33
V
1
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
mA
mA
ns
1
IOH
Output High Current
Output Low Current
1
1
IOL
38
2
1
tr1
tf1
Rise Time
Fall Time
Skew
0.5
0.5
1
2
ns
1
tsk1
500
55
ps
1
dt1
VT = 1.5 V
Duty Cycle
Jitter
45
%
1
tjcyc-cyc
VT = 1.5 V
1000
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22Ω (Rs is used in USB48MHz test only)
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz
Electrical Characteristics - Differential Jitter Parameters
Symbol
tjphasePLL
Conditions
Min
Max
86
Units
Notes
1,2
PARAMETER
TYP
PCIe Gen 1
ps (p-p)
PCIe Gen 2
10kHz < f < 1.5MHz
PCIe Gen 2
tjphaseLo
3
ps (RMS)
ps (RMS)
1,2
1,2
3.1
tjphaseHigh
1.5MHz < f < Nyquist (50MHz)
Jitter, Phase
tjphFBD1_3.2
FBD1 3.2/4G
3
ps (RMS) 1,2
ps (RMS) 1,2
11MHz to 33MHz
G
tjphFBD1_4.0
FBD1 4.8G
11MHz to 33MHz
2.5
G
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2See http://www.pcisig.com for compelte specs
1412A—12/10/07
9
Integrated
Circuit
ICS932S422C
Systems, Inc.
General SMBus serial interface information for the ICS932S422C
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
starT bit
T
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
1412A—12/10/07
10
Integrated
Circuit
ICS932S422C
Systems, Inc.
SMBus Table: SRC Output Enable Register
Byte 0
Bit 7
Pin #
NA
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
0
1
PWD
SRCCLK7 Enable
SRCCLK6 Enable
SRCCLK5 Enable
SRCCLK4 Enable
SRCCLK3 Enable
SRCCLK2 Enable
SRCCLK1 Enable
CPUCLK4
RW Disable-Hi-Z
RW Disable-Hi-Z
RW Disable-Hi-Z
RW Disable-Hi-Z
RW Disable-Hi-Z
RW Disable-Hi-Z
RW Disable-Hi-Z
RW Disable-Hi-Z
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
NA
NA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
26,27
23,24
21,22
18,19
32,31
SMBus Table: CPU, REF and 48 MHz Output Enable Register
Byte 1
Bit 7
Pin #
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
RESERVED
Output Enable
Output Enable
Type
0
1
PWD
REF1 Enable
REF0 Enable
CPUCLK3
RW Disable-Low
RW Disable-Low
RW Disable-Hi-Z
RW Disable-Hi-Z
Enable
Enable
Enable
Enable
1
1
1
1
0
1
1
54
55
36,37
39,40
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CPUCLK2
CPUCLK1
CPUCLK0
RW Disable-Hi-Z
RW Disable-Hi-Z
Enable
Enable
42,43
45,46
Spread Spectrum
Enable
CPU, SRC, PCI
Spread Off/On
RW
Spread Off
Spread On
0
Bit 0
SMBus Table: PCI and PCICLK_F Output Enable Register
Byte 2
Bit 7
Pin #
Name
PCICLK3
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
0
1
PWD
6
5
4
3
11
10
9
RW Disable-Low
RW Disable-Low
RW Disable-Low
RW Disable-Low
RW Disable-Low
RW Disable-Low
RW Disable-Low
RW Disable-Low
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
PCICLK2
PCICLK1
PCICLK0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK_F2 Enable
PCICLK_F1 Enable
PCICLK_F0 Enable
48MHz Enable
13
SMBus Table: PCICLK_F and SRC Stop Control Register
Byte 3
Bit 7
Pin #
11
10
9
26,27
23,24
21,22
18,19
-
Name
Control Function
Type
0
1
PWD
PCICLK_F2 Stop En
PCICLK_F1 Stop En
PCICLK_F0 Stop En
SRCCLK4 Stop En
SRCCLK3 Stop En
SRCCLK2 Stop En
SRCCLK1 Stop En
RW Free-Running
RW Free-Running
RW Free-Running
RW Free-Running
RW Free-Running
RW Free-Running
RW Free-Running
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
1
1
1
1
1
1
1
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Free-Running Control,
Default: not affected by
PCI/SRC_STOP
(Byte 4, bit 5)
RESERVED
1412A—12/10/07
11
Integrated
Circuit
ICS932S422C
Systems, Inc.
SMBus Table: CPU and SRC Stop and Power Down Mode Drive Control Register
Byte 4
Bit 7
Pin #
36,37
39,40
42,43
45,46
-
-
-
-
Name
Control Function
Drive Mode in PD
Drive Mode in PD
Drive mode in PD
Drive mode in PD
Type
RW
RW
RW
RW
0
1
PWD
CPUCLK3 PD Drive
CPUCLK2 PD Drive
CPUCLK1 PD Drive
CPUCLK0 PD Drive
Driven
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
SMBus Table: Output and Spread Spectrum Control Register
Byte 5
Bit 7
Pin #
32,31
SRC
SRC
-
Name
Control Function
Drive Mode in PD
Driven in STOP
Driven in PD
Type
RW
0
1
PWD
CPUCLK4 PD Drive
SRC Stop Drive Mode
SRC PD Drive Mode
Driven
Driven
Driven
Hi-Z
Hi-Z
Hi-Z
0
0
0
0
0
0
0
0
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
-
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
SMBus Table: Device ID Register
Byte 6 Pin #
Bit 7
Name
Test Mode Selection
Control Function
Test Mode Selection
Type
RW
0
Hi-Z
1
PWD
-
-
-
REF/N
0
0
0
1
Test Clock Mode Entry
Test Mode
RESERVED
1X or 2X
RW
Disable
Enable
Bit 6
Bit 5
Bit 4
REF Drive Strength
PCI_STOP Control
RW
1X
2X
54,55
Stop non-free running PC
and SRC clocks.
RW
Stop
Run
PCI, SRC
1
Bit 3
Bit 2
Bit 1
Bit 0
FS_C readback
FS_B readback
FS_A readback
FS_C
FS_B
FS_A
R
R
R
Latch
Latch
Latch
-
See 932S422 Functionality
Table
-
-
SMBus Table: Vendor & Revision ID Register
Byte 7
Bit 7
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
1
0
0
0
0
1
R
R
R
R
R
R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
R
1412A—12/10/07
12
Integrated
Circuit
ICS932S422C
Systems, Inc.
SMBus Table: Byte Count Register
Byte 8
Bit 7
Pin #
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
Control Function
Type
RW
RW
0
1
PWD
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will
RW
configure how many bytes will
be read back, default is 8
bytes.
Byte Count Programming RW
b(7:0)
RW
RW
RW
RW
(0 to 7)
BC0
SMBus Table: Device ID Register
Byte 9 Pin #
Bit 7
Name
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
Control Function
Type
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
1
1
0
0
R
R
R
R
R
R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID
(0C hex)
R
SMBus Table: M/N Programming & Control Register
Byte 10
Pin #
Name
Control Function
CPU and SRC
M/N Programming
Type
0
1
PWD
-
-
M/N_EN
RW
Disable
Enable
0
0
Bit 7
RESERVED
Bit 6
Bit 5
Spread Spectrum
Enable
Spread Spectrum
Enable
CPU
SRC
Spread Off/On
Spread Off/On
RW
RW
Spread Off
Spread Off
Spread On
Spread On
0
0
Bit 4
Bit 3
Set SRC = 96 MHz and
PCI = 32 MHz
SRC Alternate
Frequency (96% of
Nominal)
Alternate
Frequency
SRC, PCI
CPU
RW
RW
Normal
Normal
0
0
Only active if
Byte 10, bit 2 = 1
CPU Alternate
Set alternate CPU
frequency:
166 MHz to 160 MHz
333 MHz to 320 MHz
Frequency (96% of
Nominal) Only active if
latched frequency is
166 MHz or 333 MHz.
REF1 Drive Strength
Alternate
Frequency
Bit 2
1X or 2X
1X or 2X
RW
RW
See REF Drive Strength
Functionality Table
1
1
54
55
Bit 1
Bit 0
REF0 Drive Strength
1412A—12/10/07
13
Integrated
Circuit
ICS932S422C
Systems, Inc.
SMBus Table: CPU Frequency Control Register
Byte 11
Bit 7
Pin #
Name
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
Type
RW
RW
RW
RW
0
1
PWD
X
-
-
-
-
-
-
-
-
CPU N Div8
CPU N Div9
CPU M Div5
CPU M Div4
CPU M Div3
CPU M Div2
CPU M Div1
The decimal representation of
M and N Divider in Byte 11 and
12 will configure the CPU VCO
frequency. Default at power
up = latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Divider Programming RW
bit (5:0)
RW
RW
RW
CPU M Div0
SMBus Table: CPU Frequency Control Register
Byte 12
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
CPU N Div7
CPU N Div6
CPU N Div5
CPU N Div4
CPU N Div3
CPU N Div2
CPU N Div1
The decimal representation of
M and N Divider in Byte 11 and
12 will configure the CPU VCO
frequency. Default at power
up = latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Divider Programming
Byte12 bit(7:0) and
Byte11 bit(7:6)
CPU N Div0
RW
X
SMBus Table: CPU Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
CPU SSP7
CPU SSP6
CPU SSP5
CPU SSP4
CPU SSP3
CPU SSP2
CPU SSP1
CPU SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in
Byte 13 and 14 will program
the spread pecentage of CPU
Spread Spectrum
Programming bit(7:0)
SMBus Table: CPU Spread Spectrum Control Register
Byte 14
Bit 7
Pin #
Name
Control Function
Reserved
Type
0
1
PWD
0
X
X
X
X
X
X
-
-
-
-
-
-
-
-
CPU SSP14
CPU SSP13
CPU SSP12
CPU SSP11
CPU SSP10
CPU SSP9
CPU SSP8
RW
RW
RW
RW
RW
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in
Byte 13 and 14 will program
the spread pecentage of CPU
Spread Spectrum
Programming bit(14:8)
X
1412A—12/10/07
14
Integrated
Circuit
ICS932S422C
Systems, Inc.
SMBus Table: SRC Frequency Control Register
Byte 15
Bit 7
Pin #
Name
Control Function
N Divider Prog bit 8
N Divider Prog bit 9
Type
RW
RW
RW
RW
0
1
PWD
X
-
-
-
-
-
-
-
-
SRC N Div8
SRC N Div9
SRC M Div5
SRC M Div4
SRC M Div3
SRC M Div2
SRC M Div1
The decimal representation of
M and N Divider in Byte 15 and
16 will configure the SRC VCO
frequency. Default at power
up = latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M Divider Programming RW
bits
RW
RW
RW
SRC M Div0
SMBus Table: SRC Frequency Control Register
Byte 16
Bit 7
Pin #
Name
Control Function
Type
RW
RW
0
1
PWD
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
SRC N Div7
SRC N Div6
SRC N Div5
SRC N Div4
SRC N Div3
SRC N Div2
SRC N Div1
The decimal representation of
M and N Divider in Byte 15 and
16 will configure the SRC VCO
frequency. Default at power
up = latch-in or Byte 0 Rom
table. VCO Frequency =
14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
N Divider Programming RW
b(7:0)
RW
RW
RW
RW
SRC N Div0
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 17
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
SRC SSP7
SRC SSP6
SRC SSP5
SRC SSP4
SRC SSP3
SRC SSP2
SRC SSP1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in
Byte 17 and 18 will program
the spread pecentage of SRC
Spread Spectrum
Programming b(7:0)
SRC SSP0
RW
X
SMBus Table: SRC Spread Spectrum Control Register
Byte 18
Bit 7
Pin #
Name
Reserved
Control Function
Type
R
0
-
1
-
PWD
0
X
X
X
X
X
X
-
-
-
-
-
-
-
-
Reserved
SRC SSP14
SRC SSP13
SRC SSP12
SRC SSP11
SRC SSP10
SRC SSP9
RW
RW
RW
RW
RW
RW
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in
Byte 17 and 18 will program
the spread pecentage of SRC
Spread Spectrum
Programming b(14:8)
SRC SSP8
RW
X
1412A—12/10/07
15
Integrated
Circuit
ICS932S422C
Systems, Inc.
SMBus Table: CPU Programmable Output Divider Register
Byte 19
Bit 7
Pin #
Name
Control Function
Type
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
-
-
-
-
CPUDiv3
CPUDiv2
CPUDiv1
CPUDiv0
CPU Divider Ratio
Programming Bits
See CPU, SRC and PCI
Divider Ratios Table
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
X
SMBus Table: SRC and PCI Programmable Output Divider Register
Byte 20
Bit 7
Pin #
Name
PCIDiv3
PCIDiv2
PCIDiv1
PCIDiv0
SRC_Div3
Control Function
Type
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
-
-
-
-
-
-
-
-
PCI Divider Ratio
Programming Bits
See CPU, SRC and PCI
Divider Ratios Table
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
SRC_Div2
SRC_Div1
SRC_Div0
SRC_ Divider Ratio
Programming Bits
RW
RW
RW
See CPU, SRC and PCI
Divider Ratios Table
X
X
X
SMBusTable: Test Byte Register
Byte 21 Test
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Test Function
Type
RW
RW
RW
RW
RW
RW
RW
Test Result
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
-
-
-
-
-
-
-
-
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
0
0
0
0
0
0
0
RW
0
Note: Do NOT write to Bit 21. Erratic device operation will result!
1412A—12/10/07
16
Integrated
Circuit
ICS932S422C
Systems, Inc.
PD, Power Down
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
PD
1
CPU
CPU #
SRC
SRC# PCIF/PCI
USB
48MHz
Low
REF
14.318MHz
Low
Note
Normal
Normal Normal Normal
33MHz
Low
1
1
0
Iref * 2 or
Float
Float
Iref * 2
or Float
Float
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD Assertion
PD should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Byte 4 for additional information.
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
CPU, SRC and PCI Divider Ratios
REF Drive Strength Functionality
Div(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Divider
2
Byte6, Byte 10, Byte 10,
0
1
2
3
4
5
6
7
8
bit 4
bit 1
X
bit 0
X
REF1 REF0
3
5
15
4
6
10
30
8
0
1
1
1
1
1x
1x
1x
2x
2x
1x
1x
2x
1x
2x
0
0
0
1
1
0
1
1
9
12
20
60
16
24
40
120
10
11
12
13
14
15
1412A—12/10/07
17
Integrated
Circuit
ICS932S422C
Systems, Inc.
PD De-assertion
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD deassertion.
Tstable
<1.8mS
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PwrDwn#
<300µS, >200mV
Test Clarification Table
Comments
HW
SW
TEST
ENTRY REF/N or
FSLC/TES FSLB/TES
BIT
B6b6
0
X
X
HI-Z
B6b7
X
0
1
0
T_SEL
HW PIN
T_MODE
HW PIN
OUTPUT
NORMAL
HI-Z
REF/N
REF/N
0
1
1
1
X
0
0
1
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
X
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FSLC
FSLB/TEST_MODE -->low Vth input
1
0
1
X
1
1
0
REF/N
HI-Z
TEST_MODE is a real time input.
X
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B6b6.
If test mode is invoked by B6b6, only B6b7
is used to select HI-Z or REF/N
0
X
1
1
REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
1412A—12/10/07
18
Integrated
Circuit
ICS932S422C
Systems, Inc.
c
56-Lead, 300 mil Body, 25 mil, SSOP
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS
COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
22
0.635 BASIC
0.025 BASIC
α
hh xx 4455°°
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
D
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
A1
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
- CC --
56
e
SEATING
PLANE
b
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
.10 (.004)
C
Ordering Information
ICS932S422CFLF-T
Example:
ICS XXXX C F LF- T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1412A—12/10/07
19
Integrated
Circuit
ICS932S422C
Systems, Inc.
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
N
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
1
2
L
0.45
0.75
.018
.030
a
D
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
VARIATIONS
A
D mm.
D (inch)
A2
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
56
A1
Reference Doc.: JEDEC Publication 95, M O-153
- C -
10-0039
e
SEATING
PLANE
b
aaa
C
Ordering Information
ICS932S422CGLF-T
Example:
ICS XXXX C G LF- T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1412A—12/10/07
20
Integrated
Circuit
ICS932S422C
Systems, Inc.
Revision History
Rev. Issue Date Description
Page #
A
12/10/07 Initial Release
-
1412A—12/10/07
21
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