ICS93722YFLFT [ICSI]
Low Cost DDR Phase Lock Loop Zero Delay Buffer; 低成本DDR锁相环零延迟缓冲器
| 型号： | ICS93722YFLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Cost DDR Phase Lock Loop Zero Delay Buffer |
| 文件： | 总6页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS93722
Integrated
Circuit
Systems, Inc.
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Application:
Pin Configuration
DDR Zero Delay Clock Buffer
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLK_INT
N/C
VDDA
GND
VDD
CLKT2
CLKC2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
N/C
FB_INT
FB_OUTT
N/C
Product Description/Features:
•
•
•
Low skew, low jitter PLL clock driver
I2C for functional and output control
Feedback pins for input to output synchronization
•
•
Spread Spectrum tolerant inputs
3.3V tolerant CLK_INT input
SwitchingCharacteristics:
CLKT3
CLKC3
GND
•
•
•
•
•
•
•
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<110ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
28-Pin SSOP
Functionality
Block Diagram
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLKT CLKC FB_OUTT
2.5V
FB_OUTT
L
L
H
Z
H
L
H
Z
on
on
off
(nom)
Control
SCLK
CLKT0
CLKC0
2.5V
(nom)
H
L
Logic
SDATA
CLKT1
CLKC1
2.5V
(nom)
<20MHz
Z
CLKT2
CLKC2
CLKT3
CLKC3
FB_INT
PLL
CLKT4
CLKC4
CLK_INT
CLKT5
CLKC5
0539E—07/18/03
ICS93722
Pin Descriptions
PIN NUMBER
PIN NAME
GND
TYPE
DESCRIPTION
6, 11, 15, 28
PWR Ground
27, 25, 16, 14, 5, 1 CLKC(5:0)
26, 24, 17, 13, 4, 2 CLKT(5:0)
OUT
OUT
"Complementary" clocks of differential pair outputs.
"True" Clock of differential pair outputs.
3, 12, 23
VDD
PWR Power supply 2.5V
7
SCLK
CLK_INT
N/C
IN
IN
-
Clock input of I2C input, 5V tolerant input
8
"True" reference clock input
Not connected
9, 18, 21
10
VDDA
PWR Analog power supply, 2.5V
"True" Feedback output, dedicated for external feedback. It switches at
OUT
19
FB_OUTT
the same frequency as the CLK. This output must be wired to FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
20
22
FB_INT
SDATA
IN
IN
Data input for I2C serial input, 5V tolerant input
Bytes 0 to 4 are reserved power up default = 1.
Byte 6: Output Control
(1= enable, 0 = disable)
Byte 5: Output Control
(1= enable, 0 = disable)
BIT
PIN#
2, 1
4, 5
-
PWD
DESCRIPTION
CLK0 (T&C)
BIT
Bit7
Bit6
Bit5
Bit4
PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
1
1
1
1
1
1
1
1
-
-
-
-
1
1
1
1
Reserved
Reserved
Reserved
CLK2 (T&C)
CLK3 (T&C)
Reserved
Reserved
Reserved
Reserved
Reserved
-
Bit 3 13, 14
Bit 2 17, 16
24,
25
-
26,
27
-
Bit3
Bit2
Bit1
Bit0
1
1
1
1
CLK4 (T&C)
Reserved
Bit 1
Bit 0
-
-
CLK5 (T&C)
Reserved
Note: PWD = Power Up Default
0539E—07/18/03
2
ICS93722
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratings are stress specifications only and functional operation of the device at these or any other conditions above
those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Electrical Characteristics - Input / Supply / Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
SYMBOL
IIH
CONDITIONS
VIN = VDD or GND
MIN
TYP
275
MAX UNITS
µ
A
A
IIL
VIN = VDD or GND
CL = 0 pF at 133 MHz
CL = 0 pF
µ
IDD2.5
IDDPD
IOH
325
100
-18
mA
Operating Supply Current
µ
A
VDD = 2.3V, VOUT = 1V
VDD = 2.3V, VOUT = 1.2V
Output High Current
Output High Current
-43
43
mA
mA
IOL
26
High Impedance Output
Current
IOZ
VIK
VDD = 2.7V, VOUT = VDD or GND
10
A
µ
IIN = -18 mA;
Input Clamp Voltage
V
VDD = min to max, IOH = -1mA
VDD = 2.3V, IOH = -12mA
VDD = min to max, IOH = 1mA
VDD = 2.3V, IOH = 12mA
VIN = VDD or GND
2.1
2.42
1.87
0.04
0.35
V
V
VOH
High-level Output Voltage
VOL
0.1
0.6
V
Low-level Output Voltage
V
Input Capacitance1
Output Capacitance1
CIN
pF
pF
COUT
VOUT = VDD or GND
3
1. Guaranteed by design, not 100% tested in production.
0539E—07/18/03
3
ICS93722
Recommended Operating Conditions
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
VDD, AVDD
VIL
CONDITIONS
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
Analog / Core Supply Voltage
V
V
V
VDD/2 - 0.5V
Input Voltage Level
VIH
VDD/2 + 0.5V
40
IDC
Inpu Duty Cycle
Input max jitter
60
ITCYC
500
ps
Timing Requirements
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
freqop
dtin
CONDITIONS
MIN
66
TYP
MAX
200
60
UNITS
MHz
%
Operating Clock Frequency1
Input Clock Duty Cycle1
40
from VDD = 2.5V to 1% target
frequency
Clock Stabilization1
tSTAB
100
µs
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
Absolute Jitter1
SYMBOL
CONDITIONS
66 MHz
MIN
TYP
MAX
120
75
UNITS
ps
Tjabs
100 - 200 MHz
66 MHz
50
25
50
70
110
65
Cycle to cycle Jitter1,2
Tcyc-cyc
ps
100 - 200 MHz
CLK_INT to FB_INT
VT = 50%
Phase Error1
Output to output Skew1
Pulse Skew1
t(phase error)
Tskew
-150
150
100
100
50.5
51
ps
ps
ps
Tskewp
VT = 50%, 66 MHz to 100 MHz
VT = 50%, 101 MHz to 167 MHz
Single-ended 20 - 80 %
49.5
49
50
50
Duty Cycle (differential)1,3
DC
%
Rise Time, Fall Time1
tR, tF
450
550
950
ps
Load = 120Ω / 12 pF
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting output.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.
0539E—07/18/03
4
ICS93722
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address
Address
D4(H)
D5(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte Count
Dummy Command Code
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Byte 6
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component.It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the
controller.The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be
sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0539E—07/18/03
5
ICS93722
c
N
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
2.00
-
MIN
-
MAX
.079
-
L
A
A1
A2
b
0.05
1.65
0.22
0.09
.002
.065
.009
.0035
E1
E
1.85
0.38
0.25
.073
.015
.010
INDEX
AREA
c
SEE VARIATIONS
SEE VARIATIONS
D
E
7.40
5.00
8.20
5.60
.291
.197
.323
.220
1
22
E1
e
α
0.65 BASIC
0.0256 BASIC
D
L
0.55
0.95
.022
.037
A
A2
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
A1
- CC --
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
b
N
MIN
9.90
MAX
MIN
.390
MAX
.10 (.004) C
28
10.50
.413
6/1/00 Rev B
MO-150 JEDEC
Doc.# 10-0033
209 mil SSOP
Ordering Information
ICS93722yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0539E—07/18/03
6
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