ICS950223 [ICSI]
Programmable Timing Control Hub? for P4?; 可编程定时控制中心™为P4 ™
| 型号： | ICS950223 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Timing Control Hub? for P4? |
| 文件： | 总24页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS950223
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
Brookdale and Brookdale-G chipset with P4 processor.
Output Features:
Pin Configuration
*MULTSEL1/REF1 1
VDDREF 2
48 REF0/MULTSEL0**
GNDREF
47
46 VDDCPU
CPUCLKT2
•
3 - Pairs of differential CPU clocks
(differential current mode)
X1 3
X2 4
45
44 CPUCLKC2
GND 5
•
•
•
•
•
•
3 - 3V66 @ 3.3V
10 - PCI @ 3.3V
GNDCPU
PD#*
*FS2/PCICLK0 6
*FS3/PCICLK1 7
**SEL48_24#/PCICLK2 8
VDDPCI 9
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GNDCPU
IREF
1 - 48MHz @ 3.3V fixed
2 - REF @ 3.3V, 14.318MHz
1 - 48_66MHz selectable @ 3.3V fixed
1 - 24_48MHz selectable @ 3.3V
*FS4/PCICLK3 10
PCICLK4 11
PCICLK5 12
GND 13
PCICLK6 14
PCICLK7 15
PCICLK8 16
PCICLK9 17
VDDPCI 18
AVDD
Features/Benefits:
GND
TM
•
•
QuadRom frequency selection.
Programmable output frequency.
VDD3V66
3V66_0
3V66_1
Vttpwr_GD# 19
RESET# 20
GND 21
•
•
•
•
•
•
Programmable asynchronous 3V66 & PCI frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
GND
3V66_2
~*FS0/48MHz
3V66_3_48MHz/Sel66_48#**
22
*FS1/24_48MHz 23
AVDD48 24
26 SCLK
Programmable output skew.
25 SDATA
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive strength
•
•
Programmable watchdog safe frequency.
Support I2C Index read/write and block read/write
operations.
Frequency Table
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
MHz
3V66
MHz
PCI
MHz
FS4
FS3
FS2
FS1
FS0
•
Uses external 14.318MHz reference input.
0
0
0
0
0
102.00 68.00
34.00
0
0
0
0
1
105.00 70.00
108.00 72.00
111.00 74.00
114.00 76.00
117.00 78.00
120.00 80.00
123.00 82.00
126.00 72.00
130.00 74.29
136.00 68.00
140.00 70.00
144.00 72.00
148.00 74.00
152.00 76.00
156.00 78.00
160.00 80.00
164.00 82.00
166.60 66.64
170.00 68.00
175.00 70.00
180.00 72.00
185.00 74.00
190.00 76.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
36.00
37.14
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
33.32
34.00
35.00
36.00
37.00
38.00
33.40
33.40
33.40
33.40
33.34
33.33
33.33
33.33
Key Specifications:
0
0
0
0
0
0
1
1
0
1
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
Block Diagram
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL2
48MHz
24_48MHz
REF (1:0)
/ 2
X1
X2
XTAL
OSC
3V66
DIVDER
3V66_48MHz
PLL1
Spread
Spectrum
CPUCLKT (2:0)
CPUCLKC (2:0)
CPU
DIVDER
3
3
PCI
DIVDER
10 PCICLK (9:0)
Control
Logic
PD#
MULTSEL(1:0)
FS (4:0)
3V66
DIVDER
3V66 (2:0)
4
66.80
66.80
SDATA
SCLK
Vtt_PWRGD#
SEL 48_24#
SEL 66_48#
100.20 66.80
133.60 66.80
200.40 66.80
RESET#
I REF
Config.
Reg.
66.67
66.67
100.00 66.67
200.00 66.67
133.33 66.67
1
1
1
1
1
1
1
1
0
1
0496C—05/06/05
Integrated
Circuit
ICS950223
Systems, Inc.
General Description
The ICS950223 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory.
It provides all necessary clock signals for such a system.
The ICS950223 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first
tointroduceawholeproductlinewhichoffersfullprogrammabilityandflexibilityonasingleclock device.ThispartincorporatesICS's
newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C
interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal
spreadpercentage, theoutputskew, theoutputstrength, andenabling/disablingeachindividualoutputclock.TCHalsoincorporates
ICS'sWatchdogTimer technology and a reset feature to provide a safe setting under unstable system conditions.M/N control can
configureoutputfrequencywithresolutionupto0.1MHzincrement.WithalltheseprogrammablefeaturesICS's,TCHmakesmother
board testing, tuning and improvement very simple.
Pin Description
PIN
PIN
PIN
DESCRIPTION
#
NAME
TYPE
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
PWR Ref, XTAL power supply, nominal 3.3V
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin.
I/O Frequency select latch input pin / 3.3V PCI clock output.
I/O Frequency select latch input pin / 3.3V PCI clock output.
1
2
3
4
5
6
7
*MULTSEL1/REF1
I/O
VDDREF
X1
X2
GND
*FS2/PCICLK0
*FS3/PCICLK1
8
**SEL48_24#/PCICLK2
I/O Latched select input for 48/24MHz output. 0=24MHz, 1 = 48MHz / 3.3V PCI clock output.
VDDPCI
*FS4/PCICLK3
PCICLK4
PCICLK5
GND
9
PWR Power supply for PCI clocks, nominal 3.3V
I/O Frequency select latch input pin / 3.3V PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
10
11
12
13
14
15
16
17
18
PCICLK6
PCICLK7
PCICLK8
PCICLK9
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active low input.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
19
20
Vttpwr_GD#
IN
OUT
RESET#
GND
~*FS0/48MHz
*FS1/24_48MHz
AVDD48
21
22
23
24
PWR Ground pin.
I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
I/O Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
0496C—05/06/05
2
Integrated
Circuit
ICS950223
Systems, Inc.
Pin Description (Continued)
PIN PIN
PIN
DESCRIPTION
#
NAME
TYPE
25 SDATA
26 SCLK
I/O Data pin for I2C circuitry 5V tolerant
IN Clock pin of I2C circuitry 5V tolerant
Selectable 66.66MHz, 48MHz clock output / Select input for 66.66/48MHz output.
0=48mHz, 1 = 66.66MHz
27 3V66_3_48MHz/Sel66_48#** I/O
28 3V66_2
29 GND
OUT 3.3V 66.66MHz clock output
PWR Ground pin.
30 3V66_1
31 3V66_0
32 VDD3V66
33 GND
OUT 3.3V 66.66MHz clock output
OUT 3.3V 66.66MHz clock output
PWR Power pin for the 3V66 clocks.
PWR Ground pin.
34 AVDD
PWR 3.3V Analog Power pin for Core PLL
This pin establishes the reference current for the differential current-mode output pairs.
OUT This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
PWR Ground pin for the CPU outputs
35 IREF
36 GNDCPU
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
37 CPUCLKC1
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
PWR Supply for CPU clocks, 3.3V nominal
38 CPUCLKT1
39 VDDCPU
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
40 CPUCLKC0
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Asynchronous active low input pin used to power down the device into a low power
IN state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
41 CPUCLKT0
42 PD#*
OUT
43 GNDCPU
PWR Ground pin for the CPU outputs
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
44 CPUCLKC2
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
45 CPUCLKT2
OUT
46 VDDCPU
47 GNDREF
PWR Supply for CPU clocks, 3.3V nominal
PWR Ground pin for the REF outputs.
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz
reference clock.
48 REF0/MULTSEL0**
I/O
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive
0496C—05/06/05
3
Integrated
Circuit
ICS950223
Systems, Inc.
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Condition
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
CPUCLK Swing Select Functions
Reference R,
Iref=
Board Target
Output
Current
Voh @ Z,
Iref=2.32mA
MULTSEL0
MULTSEL1
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
0.5V @ 20
1.05V @ 30
0.84V @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
1
0496C—05/06/05
4
Integrated
Circuit
ICS950223
Systems, Inc.
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page.
0496C—05/06/05
5
Integrated
Circuit
ICS950223
Systems, Inc.
Table1: QuadRom Frequency Selection Table
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
MHz
3V66
MHz
PCI
MHz
Spreading
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
102.00 68.00
105.00 70.00
108.00 72.00
111.00 74.00
114.00 76.00
117.00 78.00
120.00 80.00
123.00 82.00
126.00 72.00
130.00 74.29
136.00 68.00
140.00 70.00
144.00 72.00
100.99 67.32
134.66 67.32
133.99 67.00
160.00 80.00
164.00 82.00
166.60 66.64
170.00 68.00
175.00 70.00
180.00 72.00
185.00 74.00
190.00 76.00
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
36.00
37.14
34.00
35.00
36.00
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
33.66 Center Spread
33.66 Center Spread
35.00 Center Spread
40.00
41.00
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
Spread Off
Spread Off
33.32 Center Spread
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
34.00
35.00
36.00
37.00
38.00
Spread Off
Spread Off
Spread Off
Spread Off
Spread Off
66.80
66.80
33.40 Center Spread
33.40 Center Spread
33.40 Center Spread
33.40 Center Spread
33.34 Down Spread
33.33 Down Spread
33.33 Down Spread
33.33 Down Spread
100.20 66.80
200.40 66.80
133.60 66.80
66.67
66.67
100.00 66.67
200.00 66.67
133.33 66.67
0496C—05/06/05
6
Integrated
Circuit
ICS950223
Systems, Inc.
Table1: QuadRom Frequency Selection Table Continued
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
MHz
3V66
MHz
PCI
MHz
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
114.00 76.00
115.00 76.67
116.00 77.33
117.00 78.00
118.00 78.67
119.00 79.33
120.00 80.00
121.00 80.67
122.00 81.33
123.00 82.00
125.00 83.33
127.00 84.67
129.00 86.00
131.00 87.33
133.00 88.67
135.00 90.00
152.00 76.00
153.00 76.50
154.00 77.00
155.00 77.50
156.00 78.00
157.00 78.50
158.00 79.00
159.00 79.50
160.00 80.00
161.00 80.50
162.00 81.00
163.00 81.50
164.00 82.00
165.00 82.50
144.00 72.00
148.00 74.00
38.00
38.33
38.67
39.00
39.33
39.67
40.00
40.33
40.67
41.00
41.67
42.33
43.00
43.67
44.33
45.00
38.00
38.25
38.50
38.75
39.00
39.25
39.50
39.75
40.00
40.25
40.50
40.75
41.00
41.25
36.00
37.00
0496C—05/06/05
7
Integrated
Circuit
ICS950223
Systems, Inc.
Table1: QuadRom Frequency Selection Table Continued
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
MHz
3V66
MHz
PCI
MHz
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
84.00
86.00
88.00
90.00
92.00
94.00
96.00
98.00
66.67
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
84.00
86.00
88.00
90.00
92.00
94.00
96.00
98.00
33.34
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
42.00
43.00
44.00
45.00
46.00
47.00
48.00
49.00
100.00 100.00 50.00
102.00 102.00 51.00
104.00 104.00 52.00
106.00 106.00 53.00
108.00 108.00 54.00
110.00 110.00 55.00
112.00 112.00 56.00
166.67 66.67
167.00 66.80
168.00 67.20
169.00 67.60
170.00 68.00
171.00 68.40
172.00 68.80
173.00 69.20
33.33
33.40
33.60
33.80
34.00
34.20
34.40
34.60
0496C—05/06/05
8
Integrated
Circuit
ICS950223
Systems, Inc.
Table1: QuadRom Frequency Selection Table Continued
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CPU
MHz
3V66
MHz
PCI
MHz
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
174.00 69.60
175.00 70.00
176.00 70.40
177.00 70.80
178.00 71.20
179.00 71.60
180.00 72.00
181.00 72.40
160.00 53.33
165.00 55.00
170.00 56.67
175.00 58.33
180.00 60.00
185.00 61.67
190.00 63.33
195.00 65.00
200.00 66.67
201.00 67.00
202.00 67.33
203.00 67.67
204.00 68.00
206.00 68.67
208.00 69.33
210.00 70.00
212.00 70.67
214.00 71.33
216.00 72.00
218.00 72.67
220.00 73.33
222.00 74.00
224.00 74.67
226.00 75.33
34.80
35.00
35.20
35.40
35.60
35.80
36.00
36.20
26.67
27.50
28.33
29.17
30.00
30.83
31.67
32.50
33.33
33.50
33.67
33.83
34.00
34.33
34.67
35.00
35.33
35.67
36.00
36.33
36.67
37.00
37.33
37.67
0496C—05/06/05
9
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Frequency H/W IIC
Select
FS Source
RW
Latch Inputs
IIC
0
Bit 7
-
-
-
-
-
-
-
FS6
FS5
FS4
FS3
FS2
FS1
FS0
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See Table 1: QuadRom
Frequency Selection Table
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
Type
0
1
PWD
-
-
SS1
SS0
Spread Select 1
Spread Select 0
RW
RW
See Table 2: Spread
Spectrum Table
0
0
Bit 7
Bit 6
-
SS_EN
Spread Enable Control
RW
OFF
ON
1
Bit 5
-
-
WDS_Status
Reserved
CPUT2/CPUC2
CPUT1/CPUC1
CPUT0/CPUC0
WD Soft Alarm Status
Reserved
RW
RW
RW
RW
RW
Normal
-
Disable
Disable
Disable
Alarm
-
Enable
Enable
Enable
0
1
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
45/44
38/37
41/40
Output Control
Output Control
Output Control
Table2: Spread Spectrum Select
SS1
(Byte 1 bit 7)
0
SS0
(Byte 1 bit 6)
0
Spread %
0.35%
Note
Spread 1
0
1
1
1
0
1
0.50%
0.75%
1.00%
Spread 2
Spread 3
Spread 4
I2C Table: Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1
PWD
3V66/PCI Freq Source
Select
CPU_PLL
Sync
FIX_PLL
Async
-
AEN#
RW
0
Bit 7
17
16
15
14
12
11
10
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
PCICLK9
PCICLK8
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Control
Disable
Enable
0496C—05/06/05
10
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
23
22
-
Output Control
Output Control
Geashift Reset Enable
24_48 Frequency H/W
/ IIC Select
RW
RW
RW
Disable
Disable
ON
Enable
Enable
OFF
1
1
0
Bit 7
Bit 6
Bit 5
24_48MHz
48MHz
GR_EN
-
Bit 4
24_48 FS Source
RW
Latch Inputs
IIC
0
-
Sel24_48
Output Control
Output Control
RW
RW
RW
RW
24MHz
Disable
Disable
Disable
48MHz
Enable
Enable
Enable
0
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
FS 24_48
PCICLK2
PCICLK1
PCICLK0
8
7
6
Output Control
I2C Table: Output Control Register
Byte 4
Pin #
Name
Control Function
Type
0
1
PWD
66_48 Frequency H/W
/ IIC Select
-
Bit 7
66_48 FS Source
RW
Latch Inputs
IIC
0
-
Sel66_48#
RW
RW
RW
RW
RW
RW
RW
48MHz
Disable
Disable
Disable
Disable
Disable
Disable
66.66MHz
Enable
Enable
Enable
Enable
Enable
Enable
0
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS 66_48#
3V66_0
3V66_1
REF0
REF1
3V66_3
31
30
48
1
27
28
Output Control
Output Control
Output Control
Output Control
Output Control
3V66_2
Output Control
I2C Table: 3V66 & PCICLK Asynchronous Frequency Control Register
Byte 5
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N PLL2 Div0
N PLL2 Div1
N PLL2 Div2
N PLL2 Div3
N PLL2 Div4
N PLL2 Div5
N PLL2 Div6
N PLL2 Div7
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
representation of N
PLL2 Div (0:7) + 8 is
equal to VCO divider
value for PLL2.
I2C Table: Read Back Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
WD Hard Alarm Status
Read back
Sel48_24# Read Back
Sel66_48# Read Back
FS4 Read back
-
Bit 7
WDHRB
R
-
-
-
X
-
-
-
-
-
-
-
SEL48_24RB
SEL66_48RB
FS4RB
R
R
R
R
R
R
R
-
-
-
-
-
-
-
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
FS3RB
FS2RB
FS1RB
FS3 Read back
FS2 Read back
FS1 Read back
FS0RB
FS0 Read back
0496C—05/06/05
11
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
0
1
0
0
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
I2C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Control Function
Type
0
1
PWD
-
Bit 7
WD7
RW
-
-
0
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 8 X 290ms
=2.32 seconds
-
-
-
-
-
-
-
WD6
WD5
WD4
WD3
WD2
WD1
WD0
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
1
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control Function
Type
0
1
PWD
M/N Programming
Enable
Latched
Input
IIC Prog.
B(11:17)
-
-
-
M/NEN
WDEN
RW
RW
RW
0
0
0
Bit 7
Watchdog Enable
WD Safe Frequency
Mode
Disable
Latched
FS/Byte0
Enable
WD B10
b(4:0)
Bit 6
Bit 5
WDFSEN
-
-
-
-
-
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
1
1
0
0
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to these bit will
configure the safe
frequency as Byte 0 Bit
(6:0)
0496C—05/06/05
12
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Bit 8
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal
representation of M Div
(6:0) +2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
I2C Table: VCO Frequency Control Register
Byte 12
Bit 7
Pin #
Name
N Div7
N Div6
Control Function
Type
RW
0
-
1
-
PWD
X
-
-
The decimal
representation of N Div
(8:0) + 8 is equal to
VCO divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Bit 6
RW
-
-
X
-
-
-
-
-
-
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
Reserved
Reserved
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
It is recommended to
use ICS Spread %
table for spread
programming.
SSP8
0496C—05/06/05
13
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Output Divider Control Register
Byte 15
Pin #
Name
Control Function
Type
0
1
PWD
CPU Div3
CPU Div2
CPU Div1
CPU Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
Bit 7
CPUCLK2 divider ratio
can be configured via
these 4 bits individually.
See Table 3: Divider Ratio
Combination Table
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
CPUCLK [1:0] divider
ratio can be configured
via these 4 bits
See Table 3: Divider Ratio
Combination Table
individually.
Table 3: CPU, AGP and PCI Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
11
MSB
1
2
2
4
4
8
8
0
1
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
10
11
16
24
40
56
Div
3
6
12
20
28
Div
10
11
5
10
14
Div
7
Address
Div
Address
Address
Address
LSB
I2C Table: Output Divider Control Register
Byte 16
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
3V66 [3:2] divider ratio
can be configured via
these 4 bits individually
See Table 3: Divider Ratio
Combination Table
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66 [1:0] divider ratio
can be configured via
these 4 bits individually.
See Table 3: Divider Ratio
Combination Table
I2C Table: Output Divider Control Register
Byte 17
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
3V66INV
3V66INV
CPUINV
CPUINV
PCI Div3
PCI Div2
PCI Div1
PCI Div0
3V66[3:2] Phase Invert
3V66[1:0] Phase Invert
CPU Phase Invert
RW
RW
RW
RW
RW
RW
RW
RW
Default
Default
Default
Default
Inverse
Inverse
Inverse
Inverse
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU Phase Invert
PCI divider ratio can
be configured via these
4 bits individually.
See Table 3: Divider Ratio
Combination Table
0496C—05/06/05
14
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Group Skew Control Register and Frequency Select PLL3
Byte 18
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
CPUSkw1
CPUSkw0
Reserved
Reserved
CPUSkw1
CPUSkw0
Reserved
Reserved
CPU_T2/C2 Skew
Control
RW
RW
RW
RW
RW
RW
RW
RW
See Table 4: 4-Steps Skew
Programming Table
1
0
0
0
1
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
CPU_T/C [1:0]Skew
Control
-
-
-
-
See Table 4: 4-Steps Skew
Programming Table
Reserved
Reserved
-
-
-
-
Table 4: 4-Steps Skew Programming Table
4 Step
0
1
LSB
0ps
250ps
750ps
-
-
-
0
1
500ps
-
-
MSB
I2C Table: Group Skew Control Register
Byte 19
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
3V66Skw3
3V66Skw2
3V66Skw1
3V66Skw0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
1
0
0
0
0
1
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
3V66 [3:0] Skew
Control
I2C Table: Group Skew Control Register
Byte 20
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
PCISkw1
PCISkw0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
1
0
0
0
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI Skew Control
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
0496C—05/06/05
15
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Slew Rate Control Register
Byte 21
Pin #
Name
Control Function
Type
0
1
PWD
-
PCISlw1
RW
-
-
1
Bit 7
PCICLK_2 Slew Rate
Control
-
-
-
-
-
PCISlw0
PCISlw1
PCISlw0
3V66Slw1
RW
RW
RW
RW
-
-
-
-
-
-
-
-
0
1
0
1
Bit 6
Bit 5
Bit 4
Bit 3
PCICLK [1:0] Slew
Rate Control
3V66[3:2] Slew Rate
Control
3V66Slw1
3V66Slw1
3V66Slw0
RW
RW
RW
-
-
-
-
-
-
0
1
0
Bit 2
Bit 1
Bit 0
-
-
3V66 [1:0] Slew Rate
Control
I2C Table: Slew Rate Control Register
Byte 22
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
REFSlw1
REFSlw0
PCISlw1
PCISlw0
PCISlw1
PCISlw0
PCISlw1
PCISlw0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
1
0
1
0
1
0
Bit 7
REF Slew Rate Control
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI [9:7] Slew Rate
Control
PCI [6:5] Slew Rate
Control
PCI [4:3] Slew Rate
Control
I2C Table: Slew Rate Control Register
Byte 23
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
48Slw1
48Slw0
24_48Slw1
24_48Slw0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
0
1
0
1
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
48 Slew Rate Control
24_48 Slew Rate
Control
I2C Table: Slew Rate Control Register
Byte 24
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0496C—05/06/05
16
Integrated
Circuit
ICS950223
Systems, Inc.
I2C Table: Slew Rate Control Register
Byte 25
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Transfer Mode Control
Transfer
No transfer
0
0496C—05/06/05
17
Integrated
Circuit
ICS950223
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Theseratingsarestress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sectionsofthespecificationsisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproduct
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
VIH
VIL
IIH
VSS - 0.3
V
VIN = VDD
5
mA
mA
mA
IIL1
IIL2
IDD(op)
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
-200
Operating Supply
Current
CL = 0 pF; Select @ 100MHz
217
260
40
mA
mA
Power Down
Supply Current
IDDPD
CL = 0 pF; With input address to Vdd or GND
31
Input frequency
Fi
VDD = 3.3 V;
11
27
14.31818
16
5
MHz
pF
CIN
Logic Inputs
Input Capacitance1
CINX
TSTAB
X1 & X2 pins
45
1.8
3.5
pF
Clk Stabilization1
Skew1
From VDD = 3.3 V to 1% target Freq.
1
ms
ns
TCPU-PCI VT = 1.5 V
1.5
2.5
1Guaranteed by design, not 100% tested in production.
0496C—05/06/05
18
Integrated
Circuit
ICS950223
Systems, Inc.
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
UNITS
Ω
VO = Vx
3000
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage
(abs)
VHigh
VLow
Vovs
Vuds
Statistical
660
-150
718
17
730
-7
850
150
1150
mV
mV
mV
mV
ps
measurement on single
Measurement on single
ended signal using
-450
250
Vcross(abs)
340
15
550
140
700
Variation of crossing
over all edges
VOL = 0.175V, VOH
0.525V
VOH = 0.525V VOL
0.175V
Measurement from
differential wavefrom
VT = 50%
Crossing Voltage (var) d-Vcross
=
Rise Time
Fall Time
tr
tf
175
175
45
324
=
453
700
55
ps
%
Duty Cycle
dt3
50.3
Skew
tsk3
58
56
100
150
ps
ps
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 50%
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
Output Frequency
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
33.33
MHz
V
1
IOH = -18mA
IOL = 9.4mA
2.1
16
45
VOH
1
0.4
-22
57
2
V
mA
mA
ns
ns
%
VOL
1
V
OH = 2.0 V
IOH
1
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
IOL
1
1.7
1.6
tr1
1
Fall Time
2
tf1
1
Duty Cycle
51.5
61
55
500
500
dt1
1
Skew
VT = 1.5 V
ps
ps
tsk1
1
Jitter,cycle to cyc
1Guaranteed by design, not 100% tested in production.
tjcyc-cyc
VT = 1.5 V
114
0496C—05/06/05
19
Integrated
Circuit
ICS950223
Systems, Inc.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
FO1
66.6
33
MHz
1
Ω
RDSP1 VO = VDD*(0.5)
12
55
1
VOH
IOH = -1 mA
2.4
V
V
1
VOL
IOL = 1 mA
0.55
-33
38
2
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
tf1
0.5
0.5
45
1.9
1.7
51.5
71
1
1
Fall Time
2
Duty Cycle
55
250
dt1
1
Skew
tsk1
VT = 1.5 V
ps
ps
1
tadditive VT = 1.5 V
Jitter
105 250
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN TYP MAX UNITS
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
48
MHz
1
Ω
VO = VDD*(0.5)
IOH = -1 mA
20
60
RDSP1
1
2.4
V
V
VOH
1
IOL = 1 mA
0.4
VOL
V OH@MIN = 1.0 V,
-29
1
Output High Current
Output Low Current
V
OH@MAX = 3.135 V
-23
27
mA
mA
IOH
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29
IOL
1
48MHz Rise Time
48MHz Fall Time
24MHz Rise Time
24MHz Fall Time
48 MHz Duty Cycle
24MHz Duty Cycle
48 MHz Jitter
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
1
1
2
2
ns
ns
ns
ns
%
tr1
1
1
tf1
1
1.3
1.4
52.3
50.2
2
tr1
1
1
2
tf1
1
dt1
45
45
55
55
1
VT = 1.5 V
%
dt1
1
VT = 1.5 V
139 350
123 350
ps
ps
tjcyc-cyc
1
24MHz Jitter
tjcyc-cyc
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
0496C—05/06/05
20
Integrated
Circuit
ICS950223
Systems, Inc.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
20
TYP
14.3
MAX UNITS
MHz
1
Ω
VO = VDD*(0.5)
IOH = -12mA
IOL = 9 mA
60
RDSP1
1
0.4
V
V
VOH
1
VOL
1
V
OH = 2.0 V
-33
38
mA
mA
ns
ns
%
IOH
1
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
IOL
1
1
1
2.2
2.3
4
tr1
1
Fall Time
4
tf1
1
Duty Cycle
45
54.1
129
55
dt1
1
Jitter
tjcyc-cyc
VT = 1.5 V
1000
ps
1Guaranteed by design, not 100% tested in production.
0496C—05/06/05
21
Integrated
Circuit
ICS950223
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
pin will be pulled high.With the jumper in place the pin will be
pulled low. If programmability is not necessary, than only a
singleresistorisnecessary.Theprogrammingresistorsshould
be located close to the series termination resistor to minimize
the current loop area. It is more important to locate the series
termination resistor close to the driver than the programming
resistor.
The I/O pins designated by (input/output) serve as dual signal
functionstothedevice.Duringinitialpower-up, theyactasinput
pins.Thelogiclevel(voltage)thatispresentonthesepinsatthis
timeisreadandstoredintoa5-bitinternaldatalatch. Attheend
of Power-On reset, (see AC characteristics for timing values),
the device changes the mode of operations for these pins to an
output function. In this mode the pins produce the specified
buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used.With no jumper is installed the
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0496C—05/06/05
22
Integrated
Circuit
ICS950223
Systems, Inc.
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
hh x 45°
D
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
D (inch)
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
.630
A1
48
- CC --
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
b
.10 ((..000044)) CC
300 mil SSOP Package
Ordering Information
ICS950223yFLFT
Example:
ICS XXXXXX y F LF - T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0496C—05/06/05
23
Integrated
Circuit
ICS950223
Systems, Inc.
Revision History
Rev.
Issue Date Description
5/6/2005 Added LF Ordering Information
Page #
C
23
0496C—05/06/05
24
相关型号：
ICS950227YFLFT
Processor Specific Clock Generator, 133.33MHz, PDSO56, 0.300 INCH, MO-118, SSOP-56
IDT
©2020 ICPDF网 联系我们和版权申明