ICS950910YFLF-T [ICSI]
Programmable Timing Control Hub for P4; 可编程定时控制中心的P4
| 型号： | ICS950910YFLF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Programmable Timing Control Hub for P4 |
| 文件： | 总20页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS950910
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
Features/Benefits:
VIA P4X/P4M/KT/KN266/333 style chipsets.
•
•
•
•
•
•
•
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
DDR output buffer supports up to 200MHz.
Watchdog timer technology to reset system
if system malfunctions.
Output Features:
•
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
•
•
•
•
•
•
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
3 - AGP @ 3.3V
7 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
2 - REF @ 3.3V, 14.318MHz
•
Uses external 14.318MHz crystal.
Key Specifications:
•
•
•
•
•
CPU_CS - CPUT/C: <±250ps
CPU_CS - AGP: <±250ps
CPU - DDR: <±250ps
PCI - PCI: <500ps
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Frequency Table
Pin Configuration
Bit2 Bit7 Bit6 Bit5 Bit4
CPU
AGP
MHz
PCI
Spread %
*FS0/REF0 1
GND 2
56 Vtt_PWRGD#**/REF1
FS3 FS2 FS1
FS0
MHz
MHz
55 VDDREF
54 GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
105.00
140.00
210.00
174.99
80.00
70.00
70.00
70.00
70.00
53.34
53.34
53.34
53.34
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
35.00
35.00
35.00
35.00
26.66
26.66
26.66
26.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
X1 3
X2 4
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUC_CS
48 CPUT_CS
47 GND
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1 7
*(PCI_STOP#)AGPCLK2 8
GNDAGP 9
106.66
160.00
133.33
100.00
133.33
200.00
166.66
100.00
133.33
200.00
166.66
**FS1/PCICLK_F 10
***PCICLK1 11
*MULTSEL/PCICLK2 12
GNDPCI 13
46 FBOUT
45 BUF_IN
44 DDRT0
PCICLK3 14
43 DDRC0
PCICLK4 15
42 DDRT1
VDDPCI 16
41 DDRC1
PCICLK5 17
40 VDD2.5
*(CLK_STOP#)PCICLK6 18
GND48 19
39 GND
38 DDRT2
*FS3/48MHz 20
*FS2/24_48MHz 21
AVDD48 22
37 DDRC2
Reference R,
Iref =
Board Target
Trace/Term Z
Output
Current
36 DDRT3
MULTISEL0
Voh @ Z
VDD/(3*Rr)
35 DDRC3
VDD 23
34 VDD2.5
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
50 ohms
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
GND 24
33 GND
Rr = 475 1%,
Iref = 2.32mA
IREF 25
32 DDRT4
*(PD#)RESET# 26
SCLK 27
31 DDRC4
30 DDRT5
SDATA 28
29 DDRC5
56-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
*** A 120k pull-down resistor to GND is needed on this pin.
0735A—03/18/04
Integrated
Circuit
ICS950910
Systems, Inc.
General Description
The ICS950910 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with
PC133 or DDR memory.
The ICS950910 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
FBOUT
Power Groups
Pin Number
Description
VDD
55
GND
2
Xtal, Ref
5
9
AGP [0:2], CPU digital, CPU PLL
PCI [0:5], PCI_F outputs
48MHz, Fix Digital, Fix Analog
Master clock, CPU Analog
DDR outputs
16
13
22
19
23
24
34, 40
50
33, 39
47
2.5V CPUT/C_CS output
3.3V CPUT/C & CPUOD_T/C
51
54
0735A—03/18/04
2
Integrated
Circuit
ICS950910
Systems, Inc.
Pin Description
PIN
#
PIN
PIN
TYPE
I/O
DESCRIPTION
NAME
1
Frequency select latch input pin / 14.318 MHz reference clock.
*FS0/REF0
2
PWR Ground pin.
GND
X1
X2
3
4
5
IN
Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Power supply for AGP clocks, nominal 3.3V
VDDAGP
6
7
8
I/O
I/O
I/O
Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output.
*MODE/AGPCLK0
*SEL_408/K7/AGPCLK1
CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / AGP clock output.
*(PCI_STOP#)AGPCLK2
9
GNDAGP
PWR Ground pin for the AGP outputs
10
**FS1/PCICLK_F
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
11
12
***PCICLK1
I/O
Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output.
3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock
output.
*MULTSEL/PCICLK2
I/O
13
14
15
16
17
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PWR Ground pin for the PCI outputs
OUT PCI clock output.
OUT PCI clock output.
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
18
*(CLK_STOP#)PCICLK6
#N/A #N/A
19
20
21
22
23
24
GND48
*FS3/48MHz
*FS2/24_48MHz
AVDD48
PWR Ground pin for the 48MHz outputs
I/O
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
PWR Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
PWR Power supply, nominal 3.3V
PWR Ground pin.
VDD
GND
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
25
IREF
OUT
Asynchronous active low input pin used to power down the device into a low
power state. This input is activated by the MODE selection pin / Real time
system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
26
*(PD#)RESET#
I/O
27
28
SCLK
SDATA
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
*** A 120k pull-down resistor to GND is needed on this pin.
0735A—03/18/04
3
Integrated
Circuit
ICS950910
Systems, Inc.
Pin Description (Continued)
PIN PIN
PIN
TYPE
DESCRIPTION
#
NAME
29 DDRC5
30 DDRT5
31 DDRC4
32 DDRT4
33 GND
OUT "Complimentary" Clock of differential pair output.
OUT "True" Clock of differential pair output.
OUT "Complimentary" Clock of differential pair output.
OUT "True" Clock of differential pair output.
PWR Ground pin.
34 VDD2.5
35 DDRC3
36 DDRT3
37 DDRC2
38 DDRT2
39 GND
PWR Power supply, nominal 2.5V
OUT "Complimentary" Clock of differential pair output.
OUT "True" Clock of differential pair output.
OUT "Complimentary" Clock of differential pair output.
OUT "True" Clock of differential pair output.
PWR Ground pin.
40 VDD2.5
41 DDRC1
42 DDRT1
43 DDRC0
44 DDRT0
45 BUF_IN
46 FBOUT
47 GND
PWR Power supply, nominal 2.5V
OUT "Complimentary" Clock of differential pair output.
OUT "True" Clock of differential pair output.
OUT "Complimentary" Clock of differential pair output.
OUT "True" Clock of differential pair output.
IN
Input Buffers for memory outputs.
OUT Memory feed back output.
PWR Ground pin.
48 CPUT_CS
49 CPUC_CS
50 VDDCPU2.5
51 VDDCPU3.3
OUT
True clock of differential pair 2.5V push-pull CPU outputs.
OUT Complimentary" clocks of differential pair 2.5V push-pull CPU outputs.
PWR Power pin for the CPUCLKs. 2.5V
PWR Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
52 CPUCLKC/CPUCLKODC
53 CPUCLKT/CPUCLKODT
OUT
OUT
54 GND
PWR Ground pin.
55 VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
56 Vtt_PWRGD#**/REF1
IN
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
0735A—03/18/04
4
Integrated
Circuit
ICS950910
Systems, Inc.
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page.
0735A—03/18/04
5
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Description
Bit
PWD
Bit7 Bit6 Bit5 Bit4
FS3 FS2 FS1 FS0
CPUCLK AGPCLK PCICLK
Bit2
Spread %
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
102.00
105.00
108.00
111.00
114.00
117.00
120.00
123.00
126.00
130.00
133.90
140.00
144.00
148.00
152.00
156.00
105.00
140.00
210.00
174.99
80.00
106.66
160.00
133.33
100.00
133.33
200.00
166.66
100.00
133.33
200.00
166.66
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
72.00
74.30
66.95
70.00
72.00
74.00
76.00
78.00
70.00
70.00
70.00
70.00
53.34
53.34
53.34
53.34
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
34.00
35.00
36.00
27.00
38.00
39.00
40.00
41.00
36.00
37.10
33.48
35.00
36.00
37.00
38.00
39.00
35.00
35.00
35.00
35.00
26.66
26.66
26.66
26.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
Bit
(2,7:4)
Note 1
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
Bit 3
Bit 1
0
1
1 - Spread spectrum enable
0 - Running
1 - Tristate all outputs
Bit 0
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Mode Pin - Power Management Input Control
MODE, Pin 6
(Latched Input)
Pin 26
Pin 18
Pin 8
PD#
(Input)
CPU_STOP#
(Input)
PCI_STOP#
(Input)
0
RESET#
(Output)
PCICLK5
(Output)
AGP2
(Output)
1
0735A—03/18/04
6
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin#
29
10
30
31
-
32
53, 52
48, 49
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
1
1
1
1
DDRC5 (Active/Inactive)
PCICLK_F (Active/Inactive)
DDRT5 (Active/Inactive)
DDRC4 (Active/Inactive)
(Reserved)
DDRT4 (Active/Inactive)
CPUCLKT/C_CS (Active/Inactive)
CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin#
46
18
17
15
14
12
11
53, 52
PWD
Description
FB_OUT Free running control; 1 = free running; 0 = not free running
PCICLK6 (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
CPUCLKT/C Free running control; 1 = free running; 0 = not free running
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
1
1
1
1
1
1
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
46
-
-
56
1
1
1
1
1
1
1
1
FB_OUT (Active/Inactive)
SEL 24_48, 0=24Mhz 1=48MHz
DDR free running control; 1 = free running; 0 not free running
REF1 (Active/Inactive)
CPUC/T_CS free running control; 1 = free running; 0 not free running
AGPCLK 2 (Active/Inactive)
48, 49
8
7
6
AGPCLK 1 (Active/Inactive)
AGPCLK 0 (Active/Inactive)
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
X
X
X
X
1
1
-
Latched FS3
Latched FS2
Latched FS1
Latched FS0
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
(Reserved)
-
20
21
-
1
1
REF0 (Active/Inactive)
0735A—03/18/04
7
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin#
35
36
37
38
41
42
43
44
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
DDRC3 (Active/Inactive)
DDRT3 (Active/Inactive)
DDRC2 (Active/Inactive)
DDRT2 (Active/Inactive)
DDRC1 (Active/Inactive)
DDRT1 (Active/Inactive)
DDRC0 (Active/Inactive)
DDRT0 (Active/Inactive)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Name
PWD
X
X
X
X
0
0
0
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
0
0
0
1
0
1
1
1
Device ID values will be based on individual device
"01h" in this case.
Byte 8: Byte Count Read Back Register
Bit
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
1
Note: Writing to this register will configure byte count and how
many bytes will be read back, default is 0FH = 15 bytes.
0735A—03/18/04
8
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
The decimal representation of these 8 bits correspond to X •
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
16 • 290ms = 4.6 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Description
Programming Enable bit
Program
Enable
Bit 7
0
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Software Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Bit 6
WD Enable
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Alarm
SF4
0
0
0
0
0
0
Watchdog Alarm Status 0 = normal 1= alarm status
SF3
SF2
SF1
SF0
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of Ndiv (8:0) correspond to the
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
0735A—03/18/04
9
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 13: Spread Spectrum Control Register
Bit
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Spread Spectrum (12:0) bit will program the spread
precentage. Spread precent needs to be calculated based on the
VCO frequency, spreading profile, spreading amount and spread
frequency. It is recommended to use ICS software for spread
programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
0
1
0
1
0
1
0
1
CPUCLKC/T clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
CPUCLKT/C_CS clock divider ratio can be configured
via these 4 bits individually. For divider selection table
refer to Table 1. Default at power up is latched FS
divider.
Byte 16: Output Divider Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
Reserved
Reserved
Reserved
Reserved
0
1
0
1
-
-
-
-
AGP clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
Reserved
0735A—03/18/04
10
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AGP_INV
Reserved
CPU_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
0
0
0
0
1
0
0
1
AGP Phase Inversion bit
Reserved
CPU T/C Phase Inversion bit
CPUT/C_CS Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2)
Div (3:2)
00
01
10
11
00
01
10
11
Div (1:0)
Div (1:0)
00
01
10
11
/2
/3
/5
/7
/4
/6
/8
/16
/24
/40
/56
00
01
10
11
/4
/3
/5
/9
/8
/6
/16
/12
/20
/36
/32
/24
/40
/72
/12
/20
/28
/10
/14
/10
/18
Byte 18: Group Skew Control Register
Bit
Name
PWD
Description
CPUCLKT/C_CS
Group Skew
Control
CPUCLKT/C
Group Skew
Control
AGPCLK
Group Skew
Control
These 2 bits delay the CPUCLKT/C_CS with respect to
CPUCLKT/C
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
These 2 bits delay the CPUCLKT/C clock with respect to
CPUCLKT/C_CS
Bit 7
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
1
0
1
0
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
These 2 bits delay the AGPCLK clocks with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Bit 1
Bit 0
Reserved
Reserved
X
X
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
0
1
0
0
0
Reserved
Reserved
These 4 bits can change the CPU to PCI (5:0) skew from 1.4ns -
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
PCICLK(5:0)
Group Skew
Control
0735A—03/18/04
11
Integrated
Circuit
ICS950910
Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
0
0
1
0
0
0
These 4 bits can change the CPU to PCIF skew from 1.4ns -
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bit (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
PCICLK_F
Group Skew
Control
Reserved
Reserved
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
1
0
1
0
1
CPUCLKT/C_CS
Slew Rate Control
CPUCLKT1/C1
CPUCLKT/C_CS clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
CPUCLKT1/C1 clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
CPUCLKT2/C2 clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
AGP_0 clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Slew Rate Control
CPUCLKT2/C2
Slew Rate Control
AGP_0
Slew Rate Control
Byte 22: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
1
0
1
0
1
AGP(2:1)
Slew Rate Control
PCICLK_F
Slew Rate Control
PCICLK(7:4)
Slew Rate Control
PCICLK(3:0)
AGP(2:1) clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
PCICLK_F clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(7:4) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(3:0) clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Slew Rate Control
Byte 23: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
1
0
1
0
1
REF
REF clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
IOAPIC(1:0) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
48MHz clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
Slew Rate Control
IOAPIC(1:0)
Slew Rate Control
48MHz
Slew Rate Control
24_48MHz
Slew Rate Control
24_48MHz clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
0735A—03/18/04
12
Integrated
Circuit
ICS950910
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
DD + 0.3
UNITS
V
V
VIL
IIH
VSS - 0.3
Input Low Voltage
Input High Current
0.8
5.75
200
V
VIN = VDD; Inputs with no pull-down
mA
resistors
VIN = VDD; Inputs with pull-down
IIH
A
µ
resistors
VIN = 0 V; Inputs with no pull-up
IIL1
-5.75
-200
mA
resistors
VIN = 0 V; Inputs with pull-up
resistors
Input Low Current
IIL2
A
µ
IDD3.3OP
CL = Full load; Select @ 100 MHz
CL =Full load; Select @ 133 MHz
228
220
156
159
360
mA
mA
Operating Supply Current
IDD3.3OP
IDD3.3PD
Fi
360
45
Powerdown Current
Input Frequency
Pin Inductance
IREF=2.32 mA
VDD = 3.3 V
12
mA
MHz
nH
14.318
Lpin
7
5
CIN
Logic Inputs
Output pin capacitance
X1 & X2 pins
pF
Input Capacitance1
Clk Stabilization1,2
COUT
CINX
6
pF
27
45
pF
From PowerUp or deassertion of
PowerDown to 1st clock.
TSTAB
2.1
12
12
ms
ns
ns
t
PZH,tPZL
Output enable delay (all outputs)
1
1
Delay1
t
PHZ,tPLZ
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
0735A—03/18/04
13
Integrated
Circuit
ICS950910
Systems, Inc.
Electrical Characteristics - CPUCLKC/T (Current Mode)
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source Output
Impedance
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
UNITS
VO = Vx
3000
Ω
Statistical measurement on single
ended signal using oscilloscope
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
Max Voltage
Min Voltage
VHigh
VLow
Vovs
660
-150
810
20
850
-15
380
850
150
1150
mV
mV
mV
mV
Vuds
Vcross(abs)
-450
250
Crossing Voltage (abs)
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
22
tr
tf
VOL = 0.175V, VOH = 0.525V
Rise Time
Fall Time
175
175
290
310
10
700
700
125
125
ps
ps
ps
ps
VOH = 0.525V VOL = 0.175V
d-tr
d-tf
Rise Time Variation
Fall Time Variation
10
Measurement from differential
wavefrom
dt3
Duty Cycle
45
51
55
%
tsk3
VT = 50%
Skew
16
48
100
150
ps
ps
1
VT = 50%
Jitter, Cycle to cycle
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - CPUCLKODC/T
TA = 0 - 70°C; VDD = 1.7 V +/-5%; CL = 5 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX UNITS
VOH2B
VOL2B
IOL2B
tr2B
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time1
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
1.2
0.4
V
V
18
mA
ns
ns
VOL = 20%, VOH = 80%
VOH = 80%, VOL = 20%,
0.38
0.44
0.9
0.9
Fall Time1
tf2B
Differential voltage-
VDIF
VDIF
VX
0.4
0.2
V
V
AC1
Differential voltage-
DC1
Differential Crossover
550
45
1200
1250
mV
Voltage1
Duty Cycle1
dt2B
VT = 50%
VT = 50%
51.5
140
55
%
Skew1
tsk2B
200
ps
Jitter Diff, Cycle-to-
tjcyc-cyc2B VT = VX
tjcyc-cyc2B VT = 1.0V
60
250
ps
cycle1
Jitter SE, Cycle-to-
100
250
250
ps
ps
cycle1
Jitter, Absolute1
Notes:
tjabs2B
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
0735A—03/18/04
14
Integrated
Circuit
ICS950910
Systems, Inc.
Electrical Characteristics - CPUT/C_CS
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 2 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
CONDITIONS
IOH = -12 mA
MIN
2
TYP
0.91
MAX
UNITS
V
IOL = 12mA
0.4
-19
V
VOH = 1.7V
mA
mA
ns
VOL = 0.7V
19
tr2B
VOL = 0.4V, VOH = 2.0V
1.6
55
Differential Crossover
Voltage
Vx
Note3
45
45
%
VT = 1.5V
VT = 1.5V
Duty Cycle
d-t2B
tjcyc-cyc2B
48.7
62
55
%
Jitter, Cycle to cycle
2 IOWT can be varied and is selectable thru the MULTSEL pin.
100
ps
Electrical Characteristics- DDRT/C
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH3
CONDITIONS
IOH = -11 mA
IOL = 11 mA
V OH = 2.0 V
VOL = 0.8 V
MIN
2.4
TYP
MAX
UNITS
V
V
3
0.4
-12
VOL
3
IOH
IOL
mA
3
12
650
650
45
1
20% to 80%
20% to 80%
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
660
660
50.3
102
78
950
950
53
ns
ns
%
tr3
1
Fall Time
tf3
1
Duty Cycle
Skew
dt3
1
250
250
ps
ps
tsk1
1
Jitter
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0735A—03/18/04
15
Integrated
Circuit
ICS950910
Systems, Inc.
Electrical Characteristics- PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
55
UNITS
1
33.33
MHz
Ω
FO
1
VO = VDD*(0.5)
IOH = -1 mA
12
RDSP1
1
2.4
V
VOH
1
IOL = 1 mA
0.55
-33
V
VOL
V OH@MIN = 1.0 V
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
Output High Current
Output Low Current
mA
mA
IOH
1
IOL
38
2
1
Rise Time
Fall Time
Duty Cycle
Skew
0.5
0.5
45
1.8
1.6
ns
ns
%
tr1
1
2
tf1
1
52.4
239
205
55
500
250
dt1
1
VT = 1.5 V
VT = 1.5 V
ps
ps
tsk1
1
Jitter
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics- AGP
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
55
UNITS
1
66.66
MHz
Ω
FO
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
RDSP1
1
2.4
V
VOH
1
0.55
-33
V
VOL
VOH = 1.0 V
-33
30
1
Output High Current
Output Low Current
mA
mA
IOH
VOH = 3.135 V
VOL = 1.95 V
1
IOL
VOL = 0.4 V
38
2
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Duty Cycle
Skew
0.5
0.5
45
1.5
1.28
52.9
40
ns
ns
%
tr1
1
2
tf1
1
55
500
250
dt1
1
VT = 1.5 V
ps
ps
tsk1
1
VT = 1.5 V
Jitter
113
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0735A—03/18/04
16
Integrated
Circuit
ICS950910
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX
55
UNITS
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
48
RDSP1
1
2.4
V
VOH
1
0.55
-23
V
VOL
VOH = 1.0 V
-29
29
1
Output High Current
Output Low Current
mA
mA
IOH
V
OH = 3.135 V
OL = 1.95 V
OL = 0.4 V
V
1
IOL
V
27
2
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
48MHz Rise Time
48MHz Fall Time
24MMz Rise Time
24MHz Fall Time
48 MHz Duty Cycle
48MHz Duty Cycle
48 MHz Jitter
0.5
0.5
1
1.25
1.27
1.26
1.28
52.5
51.4
124
ns
ns
ns
ns
%
tr1
1
2
tf1
1
2
tr1
1
1
2
tf1
1
45
45
55
55
350
350
dt1
1
VT = 1.5 V
%
dt1
1
VT = 1.5 V
ps
ps
tjcyc-cyc
1
VT = 1.5 V
24MHz Jitter
111
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
** USB is 180 degrees phase different to DOT
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP
14.32
MAX
UNITS
MHz
Ω
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
0.4
-23
RDSP1
1
2.4
V
VOH
1
V
VOL
V
OH = 1.0 V
OH = 3.135 V
OL = 1.95 V
OL = 0.4 V
-29
29
1
Output High Current
Output Low Current
IOH
V
mA
V
1
IOL
V
27
4
mA
ns
ns
%
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Duty Cycle
Jitter
1
1
1.92
1.92
54.1
245
tr1
1
4
tf1
1
45
55
500
dt1
1
VT = 1.5 V
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0735A—03/18/04
17
Integrated
Circuit
ICS950910
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0735A—03/18/04
18
Integrated
Circuit
ICS950910
Systems, Inc.
Power Down Waveforms
0ns
50ns
2
25ns
1
VCO Internal
CPU 100MHz
3.3V 66MHz
PCI 33MHz
PD#
REF 14.318MHZ
48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Group Offset Waveforms
0ns
10ns
20ns
30ns
40ns
Cycl e R epeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
Group Skews at Common Transition Edges
GROUP
CPU408 to CPUCS
SYMBOL
CONDITIONS
50% to 1.25V
MIN
0
TYP
75
MAX
250
UNITS
ps
CPU
CPU Open Drain to CPUCS
CPU
50% to 1.25V
0
250
SCPU-PCI
SCPU-PCI
SAGP-PCI
CPUCS to PCI
CPU408 to PCI
AGP to PCI
1.25 to 1.5V
1.25 to 1.5V
1.5 to 1.5V
0
0
2.8
3.8
4
4
ns
ns
ns
1.5
2.87
3.5
1Guaranteed by design, not 100% tested in production.
0735A—03/18/04
19
Integrated
Circuit
ICS950910
Systems, Inc.
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
18.31
MAX
18.55
MIN
.720
MAX
b
56
.730
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950910yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0735A—03/18/04
20
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