ICS95V842I [ICSI]
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz); DDR锁相环时钟驱动器（为60MHz - 220MHz的）
| 型号： | ICS95V842I |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR Phase Lock Loop Clock Driver (60MHz - 220MHz) |
| 文件： | 总9页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS95V842I
Integrated
Circuit
Systems, Inc.
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
RecommendedApplication:
1:2 DDRI Clock Driver
Pin Configuration
VDD2.5 1
DDRT0 2
DDRC0 3
GND 4
16 GND
15 DDRC1
14 DDRT1
13 VDD2.5
12 FB_INC
11 FB_INT
10 FB_OUTT
9 FB_OUTC
ProductDescription/Features:
•
•
Low skew, low jitter PLL clock driver
Feedback pins for input to output synchronization
CLK_INT 5
CLK_INC 6
AVDD 7
•
•
•
Spread Spectrum tolerant inputs
With bypass mode mux
Operating frequency 60 to 220 MHz
AGND 8
SwitchingCharacteristics:
16 pin SSOP
•
•
•
•
CYCLE - CYCLE jitter: <75ps
OUTPUT - OUTPUT skew: <60ps
Period jitter: 75ps
Half-Period jitter: 75ps
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND
GND
L
H
L
L
H
L
L
H
L
Bypassed/Off
Bypassed/Off
H
H
H
2.5V
(nom)
L
H
L
L
H
L
L
H
L
On
On
2.5V
(nom)
H
H
H
Block Diagram
FB_INT
FB_INC
FB_OUTT
FB_OUTC
PLL
CLK_INC
CLK_INT
DDRT (1:0)
DDRC(1:0)
AVDD
1234A—06/13/06
ICS95V842I
Pin Descriptions
PIN #
PIN NAME
VDD2.5
DDRT0
DDRC0
GND
CLK_INT
CLK_INC
AVDD
PIN TYPE
PWR
OUT
OUT
PWR
IN
IN
PWR
PWR
DESCRIPTION
1
2
3
4
5
6
7
8
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
AGND
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs.
9
FB_OUTC
FB_OUTT
FB_INT
OUT
OUT
IN
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs.
10
11
12
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
error.
FB_INC
IN
13
14
15
16
VDD2.5
DDRT1
DDRC1
GND
PWR
OUT
OUT
PWR
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
1234A—06/13/06
2
ICS95V842I
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V
Input clamp current: IIK (VI < 0 or VI > VDD). . . . . . +/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD) . . +/- 50mA
Continuous output current: IO (VO = 0 to VDD) . . . . +/- 50mA
Package thermal impedance, theta JA: DGG package +89°C/Ω
StorageTemperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = -40°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
IIH
MIN
TYP
MAX
UNITS
µA
µA
PARAMETER
Input High Current
Input Low Current
CONDITIONS
VI = VDD or GND
VI = VDD or GND
5
IIL
5
IDD2.5
IDDPD
IOH
∞Ω
160
100
mA
µA
mA
Operating Supply
Current
CL = 0pF, RL =
CL = 0pF, RL =
∞
Ω
Output High Current
Output Low Current
VDD = 2.3V, VOUT = 1V
-18
26
IOL
IOZ
VIK
VDD = 2.3V, VOUT = 1.2V
mA
High Impedance
Output Current
Input Clamp Voltage
VDD=2.7V, Vout=VDD or GND
10
µ
A
Iin = -18mA
-1.2
V
VDD = min to max,
V
DD - 0.1
V
V
I
OH = -1 mA
DD = 2.3V,
OH = -12 mA
VOH
High-level output voltage
V
1.7
I
VDD = min to max
IOL=1 mA
0.1
0.6
VOL
Low-level output voltage
V
DD = 2.3V
V
I
OH=12 mA
Input Capacitance1
Output Capacitance1
CIN
COUT
VI = VDD or GND
3
3
pF
pF
VI = VDD or GND
1Guaranteed by design and characterization, not 100% tested in production.
1234A—06/13/06
3
ICS95V842I
DC Electrical Characteristics
TA = -40°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
V
VDDQ, AVDD
CLK_INT, CLK_INC, FB_INC,
FB_INT
CLK_INT, CLK_INC, FB_INC,
FB_INT
Low level input voltage
High level input voltage
VIL
VIH
VIN
VID
VOD
VOX
VIX
TA
0.4
2.1
VDD/2 - 0.18
V
V
VDD/2 + 0.18
-0.3
DC input signal voltage
(note 1,2)
Differential input signal
voltage (note 3)
Differential output voltage
(note 3)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
VDD + 0.3
VDD + 0.6
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.36
V
0.7
VDD + 0.6
V
VDD/2 - 0.15
VDD/2 + 0.15
V
VDD/2 - 0.2 VDD/2 VDD/2 + 0.2
-40 85
V
Operating free-air
temperature
°C
Notes:
1 Unused inputs must be held high or low to prevent them from floating.
2 DC input signal voltage specifies the allowable DC excursion of differential input.
3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which
the differential signal must be crossing.
Timing Requirements
TA = -40°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
Max clock frequency3
Application Frequency
Range3
SYMBOL
freqop
MIN
33
MAX UNITS
233
MHz
freqApp
60
40
220
MHz
Input clock duty cycle
CLK stabilization
dtin
60
%
TSTAB
100
µs
1234A—06/13/06
4
ICS95V842I
Switching Characteristics
TA = -40°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Max clock frequency3
Application Frequency
Range3
SYMBOL
freqop
CONDITION
MIN
40
TYP
MAX UNITS
333
MHz
freqApp
60
220
MHz
Input clock duty cycle
dtin
tsl(I)
40
1
60
2
%
v/ns
µs
Input clock slew rate
CLK stabilization
TSTAB
100
Low-to high level
1
CLK_IN to any output
CLK_IN to any output
5.5
5.5
ns
ns
tPLH
propagation delay time
High-to low level propagation
delay time
1
tPHL
Output enable time
Output disable time
ten
tdis
PD# to any output
PD# to any output
5
5
ns
ns
Period jitter
tjit (per)
tjit(hper)
tsl(o)
-75
-75
1
75
75
2.5
75
50
60
ps
Half-period jitter
ps
Output clock slew rate
Cycle to Cycle Jitter
Static Phase Offset
Output to Output Skew
Over the application
frequency range
v/ns
ps
t
cyc-tcyc
t(spo)
-75
-50
ps
tskew
40
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
4. Does not include jitter.
1234A—06/13/06
5
ICS95V842I
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
/2
R = 60Ω
DD
V
(CLKC)
ICS95V842
GND
Figure 1. IBIS Model Output Load
V
DD/2
C = 14 pF
ICS95V842
-V
DD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
DD/2
V
(TT)
-V
-V
DD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
1234A—06/13/06
6
ICS95V842I
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
1
t
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(SK_O)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
t(jit_per)
tC(n)
=
-
fO
Figure 6. Period Jitter
1234A—06/13/06
7
ICS95V842I
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
(hper_n+1)
(hper_n)
1
f
o
t(jit_Hper) t(jit_Hper_n)
1
2xfO
=
-
Figure 7. Half-Period Jitter
80%
80%
V
, V
ID OD
20%
20%
Clock Inputs
and Outputs
Rise t
Fall t
sl
sl
Figure 8. Input and Output Slew Rates
1234A—06/13/06
8
ICS95V842I
16-Lead, 150 mil SSOP (QSOP)
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
1.35
0.10
--
0.20
0.18
MAX
1.75
0.25
1.50
0.30
0.25
MIN
.053
.004
--
.008
.007
MAX
.069
.010
.059
.012
.010
A
A1
A2
b
c
D
SEE VARIATIONS
SEE VARIATIONS
E
E1
e
5.80
3.80
0.635 BASIC
6.20
4.00
.228
.150
0.025 BASIC
.244
.157
L
0.40
1.27
.016
.050
N
a
ZD
SEE VARIATIONS
0° 8°
SEE VARIATIONS
SEE VARIATIONS
0° 8°
SEE VARIATIONS
VARIATIONS
D mm.
ZD
(Ref)
0.23
D (inch)
ZD
(Ref)
.009
N
MIN
4.80
MAX
5.00
MIN
.189
MAX
.197
16
Reference Doc.: JEDEC Publication 95, MO-137
10-0032
Ordering Information
ICS95V842yFILF-T
Example:
ICS XXXX y F I LF - T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
I = Industrial Temperature Range
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
1234A—06/13/06
ICS = Standard Device
9
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