5V41236NLGI8 [IDT]
4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER;
| 型号： | 5V41236NLGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER PC 输出元件 |
| 文件： | 总18页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
IDT5V41236
Recommended Applications
Features/Benefits
Four output synthesizer for PCIe Gen1/2/3
• 20-pin TSSOP/VFQFPN packages; small board footprint
• Spread-spectrum capable; reduces EMI
General Description
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
The IDT5V41236 is a PCIe Gen2/3 compliant
spread-spectrum-capable clock generator. The device has
4 differential HCSL outputs and can be used in
communication or embedded systems to substantially
reduce electro-magnetic interference (EMI). The spread
amount and output frequency are selectable via select pins.
• Power down pin; greater system power management
• OE control pin; greater system power management
• Spread% and frequency pin selection; no software
required to configure device
• Industrial temperature range available; supports
demanding embedded applications
Output Features
Key Specifications
• 4 - 0.7V current mode differential HCSL output pairs
• Cycle-to-cycle jitter < 100 ps
• Output-to-output skew < 50 ps
• PCIe Gen2 phase jitter < 3.0ps RMS
• PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
VDD
2
PD
OE
Spread
Spread
Spectrum
Circuitry
Spectrum/
Output
3
SEL[2:0]
X1
clock
selection
CLKOUTA
CLKOUTA
CLKOUTB
25 MHz
crystal or
clock
Clock
Oscillator
PLL Clock
Synthesis
CLKOUTB
CLKOUTC
X2
CLKOUTC
CLKOUTD
Optional tuning crystal
capacitors
CLKOUTD
2
Rr(IREF)
GND
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Pin Assignment (20TSSOP)
Pin Assignment (20VFQFPN)
1
2
20
19
18
17
16
15
14
13
12
11
CLKA
VDDXD
S0
CLKA
S1
S2
X1
X2
PD
3
CLKB
20 19 18 17 16
4
CLKB
VDDXD 1
S0 2
15 VDDODA
14 CLKC
5
GNDODA
VDDODA
CLKC
6
S1 3
S2 4
13 CLKC#
12 CLKD
7
X1 5
11 CLKD#
OE
GNDXD
IREF
8
CLKC
6
7
8
9 10
9
CLKD
10
CLKD
20-pin (173 mil) TSSOP
Spread Spectrum Selection Table
S2 S1 S0 Spread% Spread Type
Output
Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.5
-1.0
-1.5
Down
Down
Down
100
100
100
No Spread Not Applicable
100
-0.5
-1.0
-1.5
Down
Down
Down
200
200
200
No Spread Not Applicable
200
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Pin Descriptions
Pin
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
7
8
VDDXD
S0
Power Connect to +3.3V digital supply.
Input Spread spectrum select pin #0. See table above. Internal pull-up resistor.
Input Spread spectrum select pin #1. See table above Internal pull-up resistor.
Input Spread spectrum select pin #2. See table above. Internal pull-up resistor.
Input Crystal connection. Connect to a fundamental mode crystal or clock input.
Output Crystal connection. Connect to a fundamental mode crystal or leave open.
Input Powers down all PLLs and tri-states outputs when low. Internal pull-up resistor.
S1
S2
X1
X2
PD#
OE
Input Provides output on, tri-states output (High = enable outputs; Low = disable outputs).
Internal pull-up resistor.
9
GND
IREF
Power Connect to digital ground.
10
11
12
13
14
15
16
Output Precision resistor attached to this pin is connected to the internal current reference.
Output Selectable 100/200MHz spread spectrum differential complement output clock D.
Output Selectable 100/200MHz spread spectrum differential true output clock D.
Output Selectable 100/200MHz spread spectrum differential complement output clock C.
Output Selectable 100/200MHz spread spectrum differential true output clock C.
Power Connect to +3.3V analog supply.
CLKD#
CLKD
CLKC#
CLKC
VDDODA
GND
Power Connect to analog ground.
17
18
19
20
CLKB#
CLKB
Output Selectable 100/200MHz spread spectrum differential complement output clock B.
Output Selectable 100/200MHz spread spectrum differential true output clock B.
Output Selectable 100/200MHz spread spectrum differential complement output clock A.
Output Selectable 100/200MHz spread spectrum differential true output clock A.
CLKA#
CLKA
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Application Information
Decoupling Capacitors
Load Resistors RL
As with any high-performance mixed-signal IC, the
IDT5V41236 must be isolated from system power supply
noise to perform optimally.
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41236 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
The IDT5V41236 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41236.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01F should
be connected between VDD and GND pairs (1,9 and 15,16)
as close to the device as possible.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C -12)*2 in this equation, C =crystal
L
L
load capacitance in pf. For example, for a crystal with a 16
pF load cap, each external crystal cap would be 8 pF.
[(16-12)x2]=8.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50, then Rr = 475
(1%), providing IREF of 2.32 mA, output current (I ) is
OH
equal to 6*IREF.
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Output Structures
6*IREF
IREF
=2.3 mA
See Output Termination
Sections - Pages 3 ~ 5
RR 475
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41236.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
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Layout Guidelines
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Dimension or Value
0.5 max
0.2 max
0.2 max
33
Unit Figure
inch
inch
inch
ohm
ohm
1
1
1
1
1
Rs
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
Rs
L4
L4'
L2'
L1'
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3' L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
Rt
HCSL Output Buffer
PCI Express
Add-in Board
REF_CLK Input
L3' L3
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Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
0.45v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R4
R1a
R1b
L4
L4'
L2'
L1'
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
R6a, R6b
Cc
8.2K 5%
1K 5%
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
R6b
Cc
Cc
L4
L4'
R6a
PCIe Device
REF_CLK Input
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Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41236. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5V
All Inputs and Outputs
-0.5V to VDD+0.5V
0 to +70C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85C
-65 to +150C
125C
Junction Temperature
Soldering Temperature
260C
ESD Protection (Input)
2000V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±±%, Ambient Temperature -40 to +85C
Parameter
Symbol
Conditions
Min.
3.135
2.2
Typ.
3.3
Max.
3.465
Units
Supply Voltage
V
1
Input High Voltage
V
S0, S1, S2, OE, X1, PD#
S0, S1, S2, OE, X1, PD#
0 < Vin < VDD
VDD +0.3
V
IH
1
Input Low Voltage
V
VSS-0.3
-5
0.8
5
V
IL
2
Input Leakage Current
I
A
mA
mA
pF
pF
pF
nH
k
k
IL
Operating Supply Current
@100 MHz
I
R =33R =50, C =2 pF
113
42
125
50
7
DD
S
P
L
I
OE =Low
DDOE
Input Capacitance
Output Capacitance
X1, X2 Capacitance
Pin Inductance
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
C
5
INX
PIN
L
5
Output Impedance
Pull-up Resistance
Zo
CLK outputs
3.0
R
S0, S1, OE, S2, PD#
100
PUP
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
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AC Electrical Characteristics - CLKOUT (A:D)
Unless stated otherwise, VDD=3.3V ±±%, Ambient Temperature -40 to +85C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
25
Max.
Units
MHz
MHz
mV
mV
mV
mV
ps
Output Frequency
HCSL termination
25
200
1,2
Output Max. Voltage
V
660
-300
250
863
-53
377
45
1150
MAX
1,2
Output Min. Voltage
V
MIN
1,2
Crossing Point Voltage
Crossing Point Voltage
Absolute
550
140
125
33
1,2,4
Variation over all edges
1,3
Jitter, Cycle-to-Cycle
29
Modulation Frequency
Spread spectrum
30
32.9
237
286
73
kHz
ps
1,2
Rise Time
t
From 0.175V to 0.525V
From 0.525V to 0.175V
175
175
700
700
125
50
OR
1,2
Fall Time
t
ps
OF
1,2
Rise/Fall Time Variation
Skew between Outputs
ps
8
ps
1,3
Duty Cycle
45
52
55
%
5
Output Enable Time
All outputs
100
100
1.8
30
ns
5
Output Disable Time
All outputs
ns
Stabilization Time
t
From power-up VDD=3.3V
Settling period after spread change
1
ms
ms
STABLE
Spread Change Time
t
SPREAD
1
Test setup is R =33R =50 with C =2 pF, Rr = 475 (1%).
S
P
L
2
3
4
5
Measurement taken from a single-ended waveform.
Measurement taken from a differential waveform.
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its
PD = low.
Electrical Characteristics - Differential Phase Jitter
TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%
SPEC
Max
86
PARAMETER
Symbol
tjphaseG1
Conditions
PCIe Gen 1
Min
Typ
30
Units Notes
ps (p-p) 1,2,3
PCIe Gen 2
10kHz < f < 1.5MHz
PCIe Gen 2
ps
tjphaseG2Lo
tjphaseG2High
tjphaseG3
1
3
3.1
1
1,2,3
(RMS)
Jitter, Phase
ps
(RMS)
2.3
0.7
1,2,3
1.5MHz < f < Nyquist (50MHz)
ps
PCIe Gen 3
1,2,3
(RMS)
1Guaranteed by design and characterization, not 100% tested in production.
2See http://www.pcisig.com for complete specs
3Applies to 100MHz, spread off and 0.5% down spread only.
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Thermal Characteristics (20TSSOP)
Parameter
Symbol
Conditions
Min.
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
93
78
65
20
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Thermal Characteristics (20VFQFPN)
Parameter
Symbol
Conditions
Still air
Typ. Max. Units
Thermal Resistance Junction to
Ambient
78
70
68
37
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagram (±V41236PGG)
Marking Diagram (±V41236PGGI)
20
11
20
11
IDT5V412
36PGGI
YYWW$
IDT5V412
36PGG
YYWW$
1
10
1
10
Marking Diagram (±V41236NLGI)
Marking Diagram (±V41236NLG)
5V412
5V412
36NLGI
YWW**$
36NLG
YWW**$
Notes:
1.”**” denotes lot sequence; “YYWW” or “YWW” – Date code; “$” – mark code.
2. “G” after the two-letter package code designates RoHS compliant package.
3. “I” at the end of part number indicates industrial temperature range.
4. Bottom marking: country of origin if not USA. (PGG/I only)
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Ordering Information
Part / Order Number
5V41236PGG
Marking
see page 11
Shipping Packaging
Tubes
Package
Temperature
0 to +70C
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin TSSOP
20-pin VFQFPN
20-pin VFQFPN
20-pin VFQFPN
20-pin VFQFPN
5V41236PGG8
5V41236PGGI
5V41236PGGI8
5V41236NLG
Tape and Reel
Tubes
0 to +70C
-40 to +85C
-40 to +85C
0 to +70C
Tape and Reel
Trays
see page 11
5V41236NLG8
5V41236NLGI
Tape and Reel
Trays
0 to +70C
-40 to +85C
-40 to +85C
5V41236NLGI8
Tape and Reel
“G” after the two-letter package code are the Pb-Free configuration, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Revision History
Rev. Originator
Date
Description of Change
A
B
RDW
RDW
09/26/11 Initial release.
11/22/11 1. Changed title to “4 Output PCIe GEN1/2/3 Synthesizer”
2. Updated Differential Phase Jitter table.
C
D
LPL
J.C.
02/04/14 Typo in VFQFPN T&R ordering information and VFQFPN device markings.
06/06/16 1. Updated “Operating Supply Current” parameters/values and Conditions in DC Electrical
Characteristics table.
2. Updated RPUP, VIH and VIL conditions.
E
F
RDW
RDW
02/13/17 1. Updated Operating Supply Current [IDD] typical and maximum values.
2. Added typical values to AC Electrical Characteristics CLKOUT (A:D) table.
3. Updated typical values in Differential Phase Jitter table.
4. Updated 20-VFQFPN POD drawing.
04/04/17 1. Update “AC Electrical Characteristics - CLKOUT(A:D)” table values to latest PCIe specifications
and characterization data.
2. Updated package outline drawings.
3. Updated legal disclaimer.
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www.IDT.com
For Sales
800-345-7015 or 408-284-8200
For Tech Support
www.idt.com/go/support
Fax: 408-284-2775
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Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
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described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an
independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or
warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or
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used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated
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