5V41285PGGI8 [IDT]
2 OUTPUT PCIE GEN1/2 SYNTHESIZER;
| 型号： | 5V41285PGGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2 OUTPUT PCIE GEN1/2 SYNTHESIZER PC 输出元件 |
| 文件： | 总17页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT5V41285
Recommended Applications
Features/Benefits
2 output synthesizer for PCIe Gen1/2 and Ethernet
• 16-pin TSSOP and VFQFPN packages; small board
footprint
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
General Description
The IDT5V41285 is a PCIe Gen2 compliant clock
generator. The device has 2 differential HCSL outputs. The
output frequency is selectable via select pins.
• OE control pin; greater system power management
• Industrial temperature range available; supports
demanding embedded applications
• For PCIe Gen3 applications, see the IDT5V41315
Output Features
• 2 - Non-spread 0.7V current mode differential HCSL
output pairs
Key Specifications
• Cycle-to-cycle jitter: 80ps
• Output-to-output skew <50 ps
• PCIe Gen2 phase jitter <3.0ps RMS
• Low phase noise: 12kHz to 20MHz <6ps
Block Diagram
VDD
2
CLK0
CLK0
Control
Logic
S1:S0
2
Phase Lock Loop
CLK1
CLK1
X1/ICLK
Clock
Buffer/
25 MHz
Crystal
crystal or clock
Oscillator
X2
2
Optional tuning crystal
capacitors
Rr(IREF)
GND
OE
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
1
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Pin Assignment
1
2
3
4
5
6
7
8
VDDXD
CLK0
16
15
14
13
12
11
10
9
S0
S1
NC
X1/ICLK
X2
CLK0
16 15 14 13
GNDODA
VDDODA
CLK1
S1
NC
X1/ICLK
X2
1
2
3
4
12
11
10
9
GNDODA
VDDODA
CLK1
5V41285
CLK1
OE
5
6
7
8
GNDXD
NC
CLK1
IREF
16-pin (173 mil) TSSOP
16-pin VFQFPN
Output Select Table 1 (MHz)
S1
0
S0
0
CLK(1:0), CLK(1:0)
25M
100M
125M
200M
0
1
1
0
1
1
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
2
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Pin Descriptions
VFQFP
Pin
TSSOP
Pin
Pin
Name
Pin
Type
Pin Description
Number Number
16
1
1
2
3
4
5
6
S0
S1
Input Select pin 0. See Output Select Table 1. Internal pull-up resistor.
Input Select pin 1. See Output Select Table 1. Internal pull-up resistor.
2
NC
–
No connect.
3
X1/ICLK
X2
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output Crystal connection. Leave unconnected for clock input.
4
5
OE
Input Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
6
7
8
7
8
9
GNDXD
NC
Power Connect to ground.
–
No connect.
IREF
Output Precision resistor attached to this pin is connected to the internal current
reference.
9
10
11
12
13
14
15
16
CLK1
CLK1
Output HCSL complementary clock output 1.
Output HCSL true clock output 1.
10
11
12
13
14
15
VDDODA
GNDODA
CLK0
Power Connect to voltage supply +3.3 V for output driver and analog circuits
Power Connect to ground.
Output HCSL complementary clock output 0.
Output HCSL true clock output 0.
CLK0
VDDXD
Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
3
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
See Output Termination
Sections - Pages 3 ~ 5
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the IDT5V41285 to
meet PCI Express specifications.
RR 475
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) * 2
L
2. No vias should be used between decoupling capacitor
and VDD pin.
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50, then R = 475
R
(1%), providing IREF of 2.32 mA. The output current (I ) is
equal to 6*IREF.
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41285.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41285 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The IDT5V41285 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
4
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Layout Guidelines
SRC Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Dimension or Value
0.5 max
0.2 max
0.2 max
33
Unit Figure
inch
inch
inch
ohm
ohm
1
1
1
1
1
Rs
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
Rs
L4
L4'
L2'
L1'
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3' L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
Rt
HCSL Output Buffer
PCI Express
Add-in Board
REF_CLK Input
L3' L3
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
5
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
0.45v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R4
R1a
R1b
L4
L4'
L2'
L1'
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
R6a, R6b
Cc
8.2K 5%
1K 5%
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
Cc
L4
L4'
Cc
R6a
R6b
PCIe Device
REF_CLK Input
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
6
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.525 V
0.175 V
0.525 V
0.175 V
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
7
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41285. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDDXD, VDDODA
All Inputs and Outputs
Rating
4.6 V
-0.5 V to VDD+0.5 V
0 to +70C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85C
-65 to +150C
125C
Junction Temperature
Soldering Temperature
260C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Symbol
Conditions
Min.
3.135
2.2
Typ.
3.3
Max.
3.465
Units
V
Supply Voltage
V
1
Input High Voltage
V
S0, S1, OE, ICLK
VDD +0.3
V
IH
1
Input Low Voltage
V
S0, S1, OE, ICLK
0 < Vin < VDD
VSS-0.3
-5
0.8
5
V
IL
2
Input Leakage Current
I
A
mA
mA
pF
pF
pF
nH
k
k
IL
Operating Supply Current
@100 MHz
I
R =33R =50, C =2 pF
63
42
85
50
7
DD
S
P
L
I
OE =Low
DDOE
Input Capacitance
Output Capacitance
X1, X2 Capacitance
Pin Inductance
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
C
5
INX
PIN
L
5
Output Impedance
Pull-up Resistor
Z
CLK outputs
S0, S1, OE
3.0
O
R
100
PU
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
8
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
25
Max.
Units
MHz
MHz
MHz
mV
mV
mV
mV
ps
Output Frequency
HCSL termination
25
25
200
100
850
LVDS termination
HCSL
1,2
Output High Voltage
V
OH
1,2
Output Low Voltage
V
HCSL
-150
250
OL
1,2
Crossing Point Voltage
Crossing Point Voltage
Absolute
550
140
80
1,2,4
Variation over all edges
1,3
Jitter, Cycle-to-Cycle
Frequency Synthesis Error
All outputs
0
ppm
ps
1,2
Rise Time
t
From 0.175 V to 0.525 V
From 0.525 V to 0.175 V
175
175
700
700
125
50
OR
1,2
Fall Time
t
ps
OF
1,2
Rise/Fall Time Variation
ps
Output to Output Skew
ps
1,3
Duty Cycle
45
55
%
5
Output Enable Time
All outputs
50
50
100
100
1.8
ns
5
Output Disable Time
All outputs
ns
Stabilization Time
t
From power-up VDD=3.3 V
ms
STABLE
Note 1: Test setup is R =33R =50 with C =2 pF, Rr = 475 (1%).
S
P
L
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter
Parameter
Symbol
Conditions
Min Typ Max
Units
Notes
1,2
t
PCIe Gen1
32
0.8
2.3
86
3
ps (p-p)
jphasePLL
Jitter, Phase
t
PCIe Gen2, 10 kHz < f < 1.5 MHz
ps (RMS)
ps (RMS)
1,2
jphaseLO
t
PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz)
3.1
1,2
jphaseHIGH
Note 1. Guaranteed by design and characterization, not 100% tested in production.
Note 2. See http://www.pcisig.com for complete specs.
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
9
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Thermal Characteristics (16-TSSOP)
Parameter
Thermal Resistance Junction to
Ambient
Symbol
Conditions
Still air
Min.
Min.
Typ. Max. Units
78
70
68
37
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Thermal Characteristics (16-VFQFPN)
Parameter
Symbol
Conditions
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
63.2
55.9
51.4
65.8
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagrams
16
9
IDT5V412
85PGGI
#YYWW$
XXX
YWW$
285GI
1
8
Notes:
1. Line 1 and 2: IDT part number.
2. Line 3: # – Die revision; YYWW – Date code; $–Assembly location.
3. “G” after the two-letter package code designates RoHS compliant package.
4. “I” at the end of part number indicates industrial temperature range.
5. Bottom marking: country of origin if not USA (TSSOP only).
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
10
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Ordering Information
Part / Order Number
5V41285PGGI
Marking
See Page 10
Shipping Packaging
Tubes
Package
Temperature
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
16-pin TSSOP
16-pin TSSOP
16-pin VFQFPN
16-pin VFQFPN
5V41285PGGI8
5V41285NLGI
Tape and Reel
Trays
See Page 10
5V41285NLGI8
Tape and Reel
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Revision History
Rev.
A
Date
Originator Description of Change
04/03/12
06/05/12
J. Chao
J. Chao
New datasheet; Preliminary initial release.
B
1. Removed references to outputs for Ethernet applications in General Description and Features.
2. Updated pins 1 and 2 in pinout and pin description table from S0:S1 to NC.
3. Removed Output Select table.
4. Removed commercial grade ordering info.
C
D
06/29/12
07/23/12
J. Chao
J. Chao
1. Under output features, changed to “2 - 100MHz 0.7V current mode...”
2. Added to the beginning of the CLK1 (pin 10/11) and CLK0 (pin 14/15) descriptions “100MHz
HCSL...”
1. Updated Output Features bullet to include “Non-spread” nomenclature.
2. Added “Low Phase Noise:...” bullet to Features/Benefits.
3. Added “Output Select Table 1”.
4. Updated pin 1 & 2 descriptions to remove NC and replace with S0 and S1 respectively.
5. Updated pin descriptions for pins 1 & 2.
E
07/24/12
J. Chao
1. Removed 100MHz selection on the pins 10/11 and 14/15 descriptions, and from the Output
Features section.
2. Changed Cycle-to-cycle Jitter max. spec from 100ps to 80ps.
F
G
H
10/24/12
06/10/14
05/08/17
J. Chao
J. Chao
C.P.
Added note to page 1 Features/Benefits section stating “For PCIe Gen3 applications, see the
5V41315”
1. Added 16VFQFPN package, tables and all references.
2. Moved to Final.
Updated package outline drawings and legal disclaimer.
IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER
16
IDT5V41285
MAY 8, 2017
IDT5V41285
2 OUTPUT PCIE GEN1/2 SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
For Tech Support
www.idt.com/go/support
408-284-8200
www.idt.com/go/sales
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications
described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an
independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or
warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or
non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or
any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an
IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an
express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks
used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated
Device Technology, Inc.. All rights reserved.
相关型号：
©2020 ICPDF网 联系我们和版权申明