5V925QGI [IDT]
Clock Generator, PDSO16;
| 型号： | 5V925QGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO16 光电二极管 |
| 文件： | 总7页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE
IDT5V925
CLOCK GENERATOR
DESCRIPTION:
FEATURES:
TheIDT5V925isahigh-performance,lowskew,lowjitterphase-locked
loop(PLL)clockdriver.Itprovidesprecisephaseandfrequencyalignment
of its clock outputs to an externally applied clock input or internal crystal
oscillator. The IDT5V925 has been specially designed to interface with
Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz
clock from 25MHz input. It can also be programmed to provide output
frequencies ranging from 3.125MHz to 160MHz with input frequencies
ranging from 3.125MHz to 80MHz.
• 3V to 3.6V operating voltage
• 3.125 MHz to 160MHz output frequency range
• 4 programmable frequency outputs
• Input from fundamental crystal oscillator or external source
• Balanced Drive Outputs ±12mA
• PLL disable mode for low frequency testing
• Select inputs (S[1:0]) for divide selection (multiply ratio of 2,
3, 4, 5, 6, 7, and 8)
TheIDT5V925includesaninternalRCfilterthatprovidesexcellentjitter
characteristics and eliminates the need for external components. When
usingtheoptionalcrystalinput,thechipacceptsa10-30MHzfundamental
modecrystalwithamaximumequivalentseriesresistanceof50Ω. Theon-
chipcrystaloscillatorincludesthefeedbackresistorandcrystalcapacitors
(nominal load capacitance is 15pF).
• 5V tolerant inputs
• Low output skew/jitter
• External PLL feedback, internal loop filter
• Available in 16-pin QSOP package
APPLICATIONS:
• Ethernet/fast ethernet
• Router
• Network switches
• SAN
• Instrumentation
FUNCTIONALBLOCKDIAGRAM
S0
S1
SELECT
MODE
FB
PHASE
LOOP
VCO
0
1
VCO
DIVIDE
1/N
DETECTOR
FILTER
CLKIN
Q/N
Q0
Q1
Q2
X2
XTAL
OSC
X1
OPTIONAL
CRYSTAL
OE
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2002
1
c
2002 Integrated Device Technology, Inc.
DSC-5943/1
IDT5V925
PROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Supply Voltage to Ground
DC Output Voltage VOUT
DC Input Voltage VIN
Max
–0.5 to +7
–0.5 to VCC +0.5
–0.5 to +7
.55
Unit
V
VTERM
V
VDD
GND
Q2
1
2
3
4
5
6
7
8
S1
S0
16
15
14
13
12
11
10
V
TA = 85°C Maximum Power Dissipation
W
°C
TSTG
Storage Temperature
–65 to +150
GNDQ
VDDQ
X1
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Q1
Q0
X2
Q/N
GND
OE
CLKIN
FB
9
PINDESCRIPTION
QSOP
TOP VIEW
Pin Names
I/O
Description
CLKIN
I
I
Inputclock
(1)
X1
Crystal oscillator input. Connected to GND if
oscillatornotrequired.
(1)
X2
O
I
Crystaloscillatoroutput. Leaveunconnectedfor
clockinput.
CRYSTALSPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50Ωmaximum equivalent series resonance.
FB
PLLfeedbackinputwhichshouldbeconnectedto
Q/N output pin only. PLL locks onto positive edge
of FB signal.
S[1:0]
Q[2:0]
Q/N
OE
I
Three level divider/mode select pins. Float to MID.
Output at N*CLKIN frequency
O
O
I
Programmabledivide-by-Nclockoutput
Tri-stateoutputenable.WhenassertedHIGH,clock
outputsarehighimpedance.
VDD
PWR
PWR
PWR
PWR
Powersupplyforoutputbuffers
Groundsupplyforoutputbuffers
Power supply for PLL
GND
VDDQ
GNDQ
GroundsupplyforPLL
NOTE:
1. For best accuracy, use parallel resonant crystal specified for a load capacitance
of 15pF.
FUNCTION TABLE
Output Used for
Allowable CLKIN Range (MHz)(1,2)
OutputFrequencyRelationships
Feedback
Minimum
25/N
Maximum
Q/N
Q[2:0]
Q/N
160/N
CLKIN
CLKIN x N
NOTES:
1. Operation in the specified CLKIN frequency range guarantees that the VCO will operate in the optimal range of 25MHz to 160MHz. Operation with CLKIN outside specified
frequency ranges may result in invalid or out-of-lock outputs.
2. Q[2:0] is not allowed to be used as feedback.
2
IDT5V925
PROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
DIVIDESELECTIONTABLE(1)
S1
L
S0
L
Divide-by-N Value
FACTORY TEST (2)
Mode
L
M
H
L
2
3
PLL
PLL
L
M
M
M
H
H
H
4
PLL
M
H
L
5(3)
6
PLL
PLL
7
PLL
M
H
8
PLL
16
TEST(4)
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Factory Test Mode: operation not specified,
3. Ethernet mode (use a 25MHz input frequency and Q/N as feedback).
4. Test mode for low frequency testing. In this mode, CLKIN bypasses the VCO (VCO powered down). Frequency must be > 1MHz due to dynamic circuits in the frequency
dividers. Q[2:0] outputs are divided by 2 in test mode.
OPERATINGCONDITIONS
Symbol
VDD/VDDQ
TA
Description
Min.
3
Typ.
3.3
+25
—
Max.
3.6
+85
15
Unit
V
Power Supply Voltage
OperatingTemperature
–40
—
°C
pF
pF
CL
OutputLoadCapacitance
CIN
Input Capacitance, CLKIN, FB, OE, F = 1MHz, VIN = 0V, TA = 25°C
—
5
7
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 3.3V ±0.3V
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
—
Max
Unit
V
VIL
InputLOWVoltage
—
0.8
VIH
Input HIGH Voltage
Input HIGH Voltage
InputMIDVoltage
2
VDD - 0.6
VDD/2 - 0.3
—
—
—
V
(1)
VIHH
3-levelinputonly
—
—
VDD/2 + 0.3
0.6
V
(1)
VIMM
3-levelinputonly
—
V
(1)
VILL
InputLOWVoltage
InputLeakageCurrent
(CLKIN, FB Inputs only)
3-levelinputonly
—
V
IIN
VIN = VDD or GND, VDD = Max
- 5
—
+5
µA
VIN = VDD
HIGH Level
—
- 50
-200
- 5
—
—
+200
+50
—
I3
3-Level Input DC Current, S[1:0]
VIN = VDD/2
VIN = GND
VIN = VDD
MID Level
LOW Level
µA
—
IIH
Input HIGH Current
OutputLOWVoltage
Output HIGH Voltage
0.07
0.15
2.8
+5
µA
V
VOL
VOH
IOL = 12mA
IOH = -12mA
—
0.55
—
2.4
V
NOTE:
1. These inputs are normally wired to VCC, GND, or unconnected. If the inputs are switched in real time, the function and timing of the outputs may glitch, and the PLL may require
an additional lock time before all the datasheet limits are achieved.
3
IDT5V925
PROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
VDD = Max.
Min.
Typ.
Max
Unit
IDDQ
QuiescentSupplyCurrent
—
0.7
2
mA
CLKIN = FB = X1 = GND
S[1:0] = HH
OE = H
Alloutputsunloaded
VDD = Max., VIN = 3V
VDD = 3.6V
∆IDD
SupplyCurrentperInput
Dynamic Supply Current
—
—
1
30
µA
IDD
77
130
mA
S[1:0] =LM
OE = GND
FOUT = 60MHz
Alloutputsunloaded
NOTE:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 3.3V ±0.3V
Symbol
tR,tF
dT
Parameter
Test Conditions
0.8V to 2V
Min.
—
Typ.
0.7
—
Max.
1.5
Unit
Rise Time, Fall Time (1)
Output/Duty Cycle (1)
CLKIN to FB (1)
ns
%
VT = VDD/2
45
55
tPD
VT = VDD/2
-300
—
—
300
100
300
200
160
ps
ps
tSK
OutputtoOutputSkew(1)
VT = VDD/2; Q[2:0]
VT = VDD/2; Q/N - Q[2:0]
—
—
—
tJ
Cycle - Cycle Jitter (1)
OutputFrequency
—
—
ps
fOUT
25
—
MHz
NOTE:
1. This parameter is guaranteed by design but not tested.
INPUTTIMINGREQUIREMENTS
Symbol
tR,tF
DH
Description
Min.
—
Max.
2
Unit
ns
(1)
Maximum Input Rise and Fall Time, 0.8V to 2V
Input Duty Cycle (1)
25
75
%
fOSC
fIN
XTALOscillatorFrequency
InputFrequency
—
30
MHz
MHz
25/N
160/N
NOTE:
1. This parameter is guaranteed by design but not tested.
4
IDT5V925
PROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
TESTLOADSANDWAVEFORMS
3V
VCC
2V
CC
VTH = V
/2
0.8
0V
150Ω
1ns
1ns
OUTPUT
Input Test Waveform
15pF
150Ω
CC
V
2V
CC
VTH = V
/2
0.8
0V
AC Test Load
tR
tF
Output Waveform
HOW TO USE THE 5V925
By connecting Q/N to FB (see Figure 1), the 5V925 not only becomes
a zero delay buffer, but also a clock multiplier. With proper selection of S0
andS1,theQ0–Q2outputswillgeneratetwo,three,uptoeighttimestheinput
clockfrequency. Makesurethattheinputandoutputfrequencyspecifica-
tionsarenotviolated(refertoFunctionTable). Therearesomeapplications
where higher fan-out is required. These kinds of applications could be
addressedbyusingthe5V925inconjunctionwithaclockbuffersuchasthe
49FCT3805. Figure 2 shows how higher fan-out with different clock rates
can be generated.
The 5V925 is a general-purpose phase-locked loop (PLL) that can be
used as a zero delay buffer or a clock multiplier. It generates three outputs
at the VCO frequency and one output at the VCO frequency divided by n,
wherenisdeterminedbytheMode/FrequencySelectinputpinsS0 andS1.
The PLL will adjust the VCO frequency (within the limits of the Function
Table) to ensure that the input frequency equals the Q/N frequency.
The 5V925 can accept two types of input signal. The first is a reference
clock generated by another device on the board which needs to be
reproduced with a minimal delay between the incoming clock and output.
The second is an external crystal. When used in the first mode, the crystal
input(X1)shouldbetiedtogroundandthecrystaloutput(X2)shouldbeleft
unconnected.
FB
FB
INA
5 COPIES
OF Q/N
Q/N
Q/N
CLKIN
X2
CLKIN
Q0
Q1
Q2
5V925
49FCT3805
INB
5V925
X2
X1
5 COPIES
OF Q
X1
Q[2:0]
S0
S1
S0
S1
Figure 2
Figure 1
5
IDT5V925
PROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
Byconnectingoneofthe49FCT3505outputstotheFBinputofthe5V925
Thesecondwaytodrivetheinputofthe5V925isviaanexternalcrystal.
, the propagation delay from CLKIN to the output of the 49FCT3505 will be When connecting an external crystal to pins 5 and 6, the X2 pin must be
nearly zero. To ensure PLL stability, only one 49FCT3505 should be shorted to the CLKIN (pin 7) as shown in Figure 3. For best accuracy, a
included between Q/N and FB.
parallel resonant crystal with a crystal load capacitance rating of 15pF
should be used. To reduce the parasitic between the external crystal and
the 5V925 , it is recommended to connect the crystal as close as possible
to the X1 and X2 pins.
FB
5V925
Q/N
CLKIN
Q0
Q1
Q2
X2
X1
XTAL
OSC
S0
S1
Figure 3
One of the questions often asked is what is the accuracy of our clock
generators? Inapplicationswhereclocksynthesizersareused, theterms
frequency accuracy and frequency error are used interchangeably.
Here, frequency accuracy (or error) is based on two factors. One is the
inputfrequencyandtheotheristhemultiplicationfactor. Clockmultipliers
(or synthesizers) are governed by the equation:
output frequency error (or accuracy) is merely a function of how accurate
theinputis. Forinstance,5V925couldaccepttwoformsofinput, onefrom
a crystal oscillator (see Figure 1) and the other from a crystal (see Figure
3).Byusinga20MHzclockwithamultiplicationfactorof5(withanaccuracy
of ±30 parts per million), one can easily have three copies of 100MHz of
clock with ±30PPM of accuracy. Frequency accuracy is defined by the
followingequation:
Output Frequency = (M)* Input Frequency
N
Accuracy = (Measured Freq. – Nominal Freq.)
Nominal Frequency
where “M” is the feedback divide and “N” is the reference divide. If the
ratioofM/Nisnotaninteger, thentheoutputfrequencywillnotbeanexact
multiple of the input. On the other hand, if the ratio were a whole number,
theoutputclockwouldbeanexactmultipleoftheinput. Inthecaseof5V925,
since the reference divide (“N”) is “1”, the equation is a strong function of
thefeedbackdivide(“M”). Inaddition,sincethefeedbackisaninteger,the
where measured frequency is the average frequency over certain
number of cycles (typically 10,000) and the nominal frequency is the
desired frequency.
6
IDT5V925
PROGRAMMABLECLOCKGENERATOR
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
X
XXXX
IDT
Device Type
Process
Package
I
-40°C to +85°C (Industrial)
Q
Quarter Size Outline Package (150 mil.)
Programmable Clock Generator
5V925
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
logichelp@idt.com
(408) 654-6459
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
7
相关型号：
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PLL Based Clock Driver, 5V Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32
IDT
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