709149S8PFGI [IDT]
HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM;
| 型号： | 709149S8PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM 静态存储器 |
| 文件： | 总10页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT709149S
HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS PIPELINED
DUAL-PORT SRAM
Features
◆
◆
Architecture based on Dual-Port SRAM cells
Synchronous operation
– Allows full simultaneous access from both ports
High-speed clock-to-data output times
– Commercial:8/10/12ns(max.)
– Industrial: 10ns (max.)
– 4ns setup to clock, 1ns hold on all control, data, and
◆
address inputs
– Data input, address, and control registers
– Fast 8ns clock to data out
◆
◆
◆
◆
◆
Low-power operation
TTL-compatible, single 5V (±10%) power supply
Clock Enable feature
– IDT709149S
Active: 1500mW (typ.)
Guaranteed data output hold times
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Standby:75mW(typ.)
◆
◆
4K X 9 bits
◆
13ns cycle time, 76MHz operation in pipeline mode
– Self-timed write allows for fast cycle times
Green parts available, see ordering information
Functional Block Diagram
I/O0-8L
I/O0-8R
WRITE
WRITE
MEMORY
LOGIC
LOGIC
FT/PIPED
R
ARRAY
0/1
0
SENSE
AMPS
SENSE
AMPS
1
DECODERDECODER
REG
en
REG
en
OE
CLK
CLKEN
L
OE
CLK
CLKEN
R
L
R
L
R
Self-
Self-
timed
Write
Logic
timed
Write
Logic
R/WR
R/W
L
REG
REG
CEL
CER
A0L-A11L
A0R-A11R
3494 drw 01
APRIL 2015
1
DSC-3494/7
©2015 Integrated Device Technology, Inc.
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TheIDT709149utilizesa9-bitwidedatapathtoallowforparityatthe
user's option. This feature is especially useful in data communication
applications where it is necessary to use a parity bit for transmission/
receptionerrorchecking.
Description
The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port
SRAM.ThememoryarrayisbasedonDual-Portmemorycells toallow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
providedbythisapproachwillallowsystemstobedesignedwithveryshort
cycle times. This device has been optimized for applications having
unidirectionaldatafloworbi-directionaldataflowinbursts,byutilizinginput
dataregisters.
FabricatedusingCMOShigh-performancetechnology,theseDual-
Portstypicallyoperateononly800mWofpowerat maximumhigh-speed
clock-to-data output times as fast as 8ns. An automatic power down
feature,controlledby CE,permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
The IDT709149 is packaged in an 80-pin TQFP.
Pin Configurations(1,2,3)
Reference
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
N/C
1
2
60
N/C
59
A
A
A
A
6L
7L
8L
9L
A
A
A
7R
8R
9R
3
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
4
5
A
A
10R
6
A
A
10L
11R
7
11L
N/C
IDT709149PF
8
N/C
OE
OE
R
(4)
PN80
9
L
FT/PIPED
R
10
11
12
13
14
15
16
17
18
19
20
V
CC
CC
GND
80-Pin TQFP
GND
V
(5)
Top View
R/W
L
N/C R
R/W
N/
N/C
C
N/C
CE
L
CER
GND
I/O8L
I/O7L
I/O6L
N/C
GND
I/O8R
I/O7R
I/O6R
N/C
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3494 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4, This package code is used to reference the package diagram.
5. This text does not indicate the orientaion of the actual part-marking.
6.42
2
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum OperatingTemperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
GND
Vcc
(2)
Ambient Temperature
0OC to +70OC
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
Commercial
Industrial
0V
0V
5.0V
5.0V
+
+
10%
(2)
TERM
V
Terminal Voltage
-0.5 to VCC
-55 to +125
V
oC
-40OC to +85OC
10%
3494 tbl 02
Temperature
Under Bias
T
BIAS
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Storage
-65 to +150
50
oC
T
STG
Temperature
IOUT
DC Output Current
mA
3494 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating
Conditions
Symbol
Parameter
Supply Voltage
Min.
4.5
Typ.
Max. Unit
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
V
CC
5.0
5.5
V
V
V
GND
Ground
0
0
____
0
V
IH
Input High Voltage
Input Low Voltage
2.2
-0.5(1)
6.0(2)
0.8
____
V
IL
V
3494 tbl 03
Capacitance (TA = +25°C, f = 1.0MHz)
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Symbol
Parameter
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
C
IN
Input Capacitance
Output Capacitance
V
8
9
pF
COUT
V
pF
3494 tbl 04
NOTES:
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
709149S
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Test Conditions
CC = 5.5V, VIN = 0V to VCC
OUT = 0V to VCC
Min.
Max.
Unit
µA
µA
V
___
___
___
|
V
V
10
10
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
OL
I
OL = +4mA
0.4
___
V
OH
I
OH = -4mA
2.4
V
3494 tbl 05
NOTE:
1. At VCC < 2.0V, input leakages are undefined
6.342
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(4) (VCC = 5V ± 10%)
709149S8
709149S10
709149S12
Com'l Only
Com'l Only
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
IND
Typ.
200
Max.
320
Typ.
Max.
310
340
150
175
220
250
Typ.
180
Max.
300
Unit
ICC
Dynamic Operating
Current
mA
190
190
90
CE
L
and CE = VIL,
R
Outputs(1D) isabled
____
____
____
____
(Both Ports Active)
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
100
____
150
____
85
____
140
____
mA
mA
mA
CE and CE = VIH
R
f = LfMAX
(1)
90
(3)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
180
230
170
170
160
210
CE"A" = V and CE = VIH
Active PoIrLt Outputs"BD"isabled,
(1)
____
____
____
____
f=fMAX
ISB3
Full Standby Current
(Both Ports - All
CEL and
COM'L
IND
5
15
5
5
15
20
5
15
CE > V - 0.2V,
CMOS Level Inputs)
V
R> VCCCC- 0.2V or
VIN < 0.2V, f = 0(2)
____
____
____
____
ISB4
Full Standby Current
(One Port - All
mA
COM'L
IND
170
220
160
160
210
240
150
200
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(3)
____
____
____
____
CMOS Level Inputs)
V
IN > VCC - 0.2V or V < 0.2V
Active Port Outputs DIiNsabled,
(1)
f = fMAX
3494 tbl 06
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ).
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
8
7
6
9pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
3494 tbl 07
5V
5V
5
4
3
2
1
∆tCD
(Typical, ns)
893Ω
893Ω
DATAOUT
DATAOUT
30pF
5pF*
347Ω
347Ω
0
,
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
3494 drw 04
-1
3494 drw 03
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
3494 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
4
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range—
(Read and Write Cycle Timing)
709149S8
709149S10
Com'l
709149S12
Com'l Only
Com'l Only
& Ind
Symbol
Parameter
Clock Cycle Time (Flow-Through)(3)
Clock Cycle Time (Pipelined)(3)
Clock High Time (Flow-Through)(3)
Clock Low Time (Flow-Through)(3)
Clock High Time (Pipelined)(3)
Clock Low Time (Pipelined)(3)
Clock to Data Valid (Flow-Through)(3)
Clock to Data Valid (Pipelined)(3)
Registered Signal Set-up Time
Registered Signal Hold Time
Min.
16
13
6
Max.
Min.
20
15
7
Max.
Min.
20
16
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
CD1
CD2
t
t
t
6
7
8
t
6
6
6
t
6
____
6
____
6
____
t
12
15
20
____
____
____
t
8
____
10
____
12
____
tS
4
1
1
4
1
1
5
1
1
____
____
____
____
____
____
____
____
____
tH
t
DC
CKLZ
CKHZ
OE
OLZ
OHZ
SCK
HCK
CWDD
Data Output Hold After Clock High
(1,2)
t
Clock High to Output Low-Z
2
____
2
____
2
____
(1,2)
t
Clock High to Output High-Z
7
7
9
____
____
____
t
Output Enable to Output Valid
Output Enable to Output Low-Z(1,2)
8
____
8
____
10
____
t
0
____
0
____
0
____
(1,2)
t
Output Disable to Output High-Z
7
____
7
____
9
____
t
Clock Enable, Disable Set-Up Time
Clock Enable, Disable Hold Time
4
4
5
____
____
____
t
1
____
1
____
1
____
t
Write Port Clock High to Read Data Delay
25
30
35
ns
3494 tbl 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The Pipelined output parameters (tCYC2, tCD2) always apply to the Left Port. The Right Port uses the Pipelined tCYC2 and tCD2 when FT/PIPEDR = VIH and the Flow-
Through parameters (tCYC1, tCD1) when FT/PIPEDR = VIL.
6.542
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output on Right Port
(FT/PipedR = VIL)
t
CYC1
t
CH1
tCL1
CLK
CLKEN
CE
tSCK
t
HCK
tSCK
tS
t
H
R/W
ADDRESS
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCKHZ
t
CD1
Qn
Qn + 1
Qn + 1
(1)
tCKLZ
(1)
(1)
tOHZ
tOLZ
tOE
OE
3494 drw 06
Timing Waveform of Left Port Write to Flow-Through Right Port Read
(FT/PipedR = VIL)(2,3)
CLK "L"
R/W "L"
NO
ADDR "L"
DATA IN "L"
CLK "R"
MATCH
VALID
MATCH
VALID
t
CCS
R/W "R"
NO
MATCH
ADDR "R"
DATA OUT "R"
NOTES:
MATCH
tCWDD
tCD1
VALID
VALID
tDC
3494 drw 07
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CEL = CER = VIL, CLKENL = CLKENR = VIL
3. OE = VIL for the reading port, port 'R'.
6.42
6
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(Left Port; Right Port when FT/PipedR = VIH)(3)
tCYC2
tCH2
tCL2
CLK
tS
tH
tH
tS
CE
R/W
tH
tS
An
An + 1
An + 2
Qn
An + 3
ADDRESS
(1 Latency)
tDC
tCD2
tCD2
DATAOUT
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
(1)
t
OHZ
tOLZ
OE (2)
tOE
3494 drw 08
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. CLKENL and CLKENR = VIL.
6.742
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)
tCYC2
tCH2
tCL2
CLK
CE
t
S
tH
t
S
tH
R/W
tS
tH
An + 4
An + 3
An
S
An +1
An + 2
An + 2
ADDRESS
t
tH
tS
t
H
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
t
CKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(3)
WRITE
READ
3494 drw 09
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
t
CYC2
tCH2
tCL2
CLK
tS
tH
CE
t
S
tH
R/W
t
S
tH
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
DATAIN
tS
tH
t
S
tH
Dn + 2
(1)
tCKLZ
tCD2
tCD2
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
WRITE
READ
READ
3494 drw 10
NOTES:
1. Transitionismeasured0mVfromLoworHigh-impedancevoltagewiththeOutputTestLoad(Figure2).
2. Outputstate(High,Low,orHigh-impedance)isdeterminedbythepreviouscyclecontrolsignals.
3. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
8
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
possible realized cycle times. Clock enable inputs are provided to stall
the operation of the address and data input registers without introduc-
ing clock skew for very fast interleaved memory applications.
A HIGH on the CE input for one clock cycle will power down the
internal circuitry to reduce static power consumption.
TheIDT709149providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide very short set-up and hold times
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare
clockedontherisingedgeoftheclock signal. Anasynchronousoutput
enable is provided to ease asynchronous bus interfacing.
When piplelined mode is enabled, two cycles are required with
CE LOW to reactivate the outputs.
The internal write pulse width is dependent only on the low to high
transitions of the clock signal to initiate a write allowing the shortest
Truth Table I: Read/Write Control(1)
Inputs
Synchronous(3)
Outputs
Asynchronous
Mode
CLK
↑
R/W
X
I/O0-8
High-Z
DATAIN
DATAOUT
High-Z
CE
H
L
OE
X
Deselected—Power Down
L
X
Selected and Write Enable
↑
L
H
L
Read Selected and Data Output Enabled Read (1 Latency)
Data I/O Disabled
↑
X
X
H
↑
3494 tbl 09
Truth Table II: Clock Enable Function Table(1)
Inputs
Register Inputs
Register Outputs(4)
ADDR DATAOUT
Operating Mode
Load "1"
CLK(3)
ADDR
DATAIN
CLKEN(2)
L
L
H
L
H
L
H
L
H
L
↑
↑
↑
X
Load "0"
Hold (do nothing)
H
H
X
X
X
X
NC
NC
NC
NC
3494 tbl 10
NOTES:
1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage
level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = VIL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOW-
to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK.
4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
6.942
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
A
999
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
PF
Green
80-pin TQFP (PN80)
Commercial Only
Commercial & Industrial
Commercial Only
8
10
12
Speed in nanoseconds
Standard Power
S
709149
36K (4K x 9-Bit) Synchronous
Pipelined Dual-Port RAM
3494 drw 11
NOTE:
1. Contactyourlocalsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
Datasheet Document History
3/8/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
6/3/99:
9/1/99:
RemovedPreliminary
11/10/99:
5/24/00:
Replaced IDT logo
Page 3 Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
01/24/02:
Page 2 Added date revision for pin configuration
Page 3, 4 & 5 Removed Industrial temp footnote from all tables
Page4AddedIndustrialtempto10nsspeedinthecolumnheadingandvaluesofDCElectricalCharacteristics
Page5CorrectedatypointhecolumnheadingofACElectricalCharacteristics
Page5AddedIndustrialtempto10nsspeedinthecolumnheadingofACElectricalCharacteristics
Page10AddedIndustrialtempto10nsofferinginorderinginformation
Pages 1& 10 Replaced TM logo with ® logo
01/29/09:
04/08/15:
Page 10 Removed "IDT" from orderable part number
Page 2 RemovedIDTinreferencetofabrication
Page 2 &10 The package code PN80-1 changed to PN80 to match standard package codes
Page 4 CorrectedtypointheTypicalOutputDerating(LumpedCapitiveLoad)diagram
Page 10 AddedTapeandReelandGreenindicatorswiththeirfootnoteannotationstotheOrderingInformation
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
408-284-2794
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
10
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