71T016S12PH18 [IDT]
TSOP-44, Reel;
| 型号： | 71T016S12PH18 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSOP-44, Reel |
| 文件： | 总9页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance
Information
IDT71T016SA
2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Features
Description
◆
64K x 16 advanced high-speed CMOS Static RAM
TheIDT71T016isa1,048,576-bithigh-speedStaticRAMorganized
as64Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds.
◆
Equal access and cycle times
— Commercial:10/12/15/20ns
— Industrial:12/15/20ns
One Chip Select plus one Output Enable pin
◆
◆
Bidirectional data inputs and outputs directly
TheIDT71T016has anoutputenablepinwhichoperates as fastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71T016areLVTTL-compatibleandoperationisfroma
single2.5Vsupply.Fullystaticasynchronouscircuitryisused,requiring
noclocks orrefreshforoperation.
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 2.5V power supply
◆
◆
◆
◆
Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball
The IDT71T016 is packaged in a JEDEC standard a 44-pin Plastic
SOJ, 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Plastic FBGA packages
Functional Block Diagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 – A15
I/O15
High
Byte
I/O
8
8
Chip
Enable
Buffer
CS
Buffer
I/O8
Sense
Amps
and
Write
Drivers
16
64K x 16
Memory
Array
Write
Enable
Buffer
WE
I/O7
I/O0
Low
Byte
I/O
8
8
Buffer
BHE
BLE
Byte
Enable
Buffers
5326 drw 01
AUGUST 2001
1
©2001 IntegratedDeviceTechnology,Inc.
DSC-5326/00
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
1
2
3
4
5
6
A
B
C
D
E
A0
A1
A2
NC
BLE
OE
A4
A3
A2
A1
A0
CS
1
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
A6
I/O8
I/O9
VSS
VDD
I/O14
I/O15
NC
A3
A5
A4
A6
I/O0
I/O2
VDD
VSS
I/O6
I/O7
BHE
I/O10
I/O11
I/O12
I/O13
NC
CS
I/O1
I/O3
I/O4
I/O5
WE
A11
3
A7
4
OE
5
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VDD
I/O11
I/O10
I/O9
I/O8
NC
6
I/O0
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
7
NC
NC
A14
A12
A9
A7
8
9
NC
A15
A13
A10
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
F
G
H
A8
NC
5326 tbl 02a
A8
FBGA (BF48-1)
Top View
A9
A10
A11
Pin Description
NC
A0 – A15
Address Inputs
Input
5326 drw 02
Chip Select
Input
Input
Input
Input
Input
I/O
CS
TSOP
Top View
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
2.5V Power
WE
OE
BHE
BLE
I/O0 – I/O15
VDD
Power
Gnd
VSS
Ground
5326 tbl 01
Truth Table(1)
CS
H
L
OE
X
L
WE
X
H
H
H
L
BLE
BHE
X
H
L
I/O0-I/O7
High-Z
I/O8-I/O15
Function
X
L
High-Z
High-Z
Deselected – Standby
OUT
DATA
Low Byte Read
High Byte Read
Word Read
OUT
DATA
L
L
H
L
High-Z
OUT
DATA
OUT
DATA
L
L
L
IN
DATA
IN
DATA
L
X
X
X
H
X
L
L
Word Write
IN
DATA
L
L
L
H
L
High-Z
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
IN
DATA
L
L
H
X
H
High-Z
High-Z
High-Z
L
H
X
X
H
High-Z
High-Z
L
5326 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.42
2
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage
Symbol
Rating
Value
Unit
VDD
Supply Voltage Relative
to VSS
–0.3 to +3.6
V
SS
DD
V
Grade
Temperature
0°C to +70°C
-40°C to +85°C
V
Commercial
Industrial
0V
0V
See Below
Terminal Voltage Relative
to VSS
–0.3 to VDD+0.3
V
VIN, VOUT
See Below
oC
oC
W
5326 tbl 04
TBIAS
TSTG
PT
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.25
Recommended DC Operating
Conditions
IOUT
DC Output Current
50
mA
Symbol
Parameter
Min.
0
Typ.
Max.
0
Unit
5326 tbl 03
NOTE:
DD
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
Vss
Ground
0
V
____
IH
Input Low Voltage
DD
____
V
IL
–0.3
0.7
V
Capacitance
(TA = +25°C, f = 1.0MHz)
5326 tbl 05
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
6
7
pF
CI/O
pF
5326 tbl 06
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
DCElectrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71T016SA
Symbol
|ILI|
Parameter
Input Leakage Current
Test Condition
VDD = Max., VIN = VSS to VDD
VDD = Max., CS = VIH, VOUT = VSS to VDD
IOL = 2.0mA, VDD = Min.
Min.
Max.
Unit
µA
µA
V
___
___
___
5
5
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
VOL
0.7
___
VOH
IOH = 2.0mA, VDD = Min.
1.7
V
5326 tbl 07
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71T016SA10
Com'l
160
71T016SA12
71T016SA15
71T016SA20
Parameter
Symbol
Com'l
Ind
Com'l
130
Ind
Com'l
Ind
Unit
Max.
150
120
160
130
120
110
120
Dynamic Operating Current
ICC
mA
(3)
LC
DD
MAX
CS < V , Outputs Open, V = Max., f = f
____
____
____
Typ.(4)
125
110
Dynamic Standby Power Supply Current
ISB
45
10
40
15
45
15
35
15
35
15
30
15
30
15
mA
(3)
HC
DD
MAX
CS > V , Outputs Open, V = Max., f = f
Full Standby Power Supply Current (static)
ISB1
mA
(3)
HC
DD
CS > V , Outputs Open, V = Max., f = 0
5326 tbl 8
NOTES:
1. Allvaluesaremaximumguaranteedvalues.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are measured at 2.5V, 25°C and with equal read and write cycles.
6.42
3
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
0V to 2.5V
1.5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
(VDD/2)
(VDD/2)
See Figure 1, 2 and 3
5326 tbl 09
2.5V
AC Test Loads
320
Ω
Ω
+1.25V
50Ω
OUT
DATA
5pF*
350
Z0 = 50Ω
I/O
5326 drw 04
30pF
5326 drw 03
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
5
4
3
•
∆tAA, tACS
(Typical, ns)
•
•
2
1
•
•
•
·
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
5326 drw 05
Figure 3. Output Capacitive Derating
6.42
4
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71T016SA10(2)
71T016SA12
71T016SA15
71T016SA20
Symbol
Parameter
Min.
Max.
Min. Max.
Min. Max.
Min. Max.
Unit
READ CYCLE
____
____
____
____
RC
t
Read Cycle Time
10
12
15
20
ns
ns
ns
ns
____
____
____
____
AA
t
Address Access Time
10
12
15
20
____
____
____
____
ACS
t
Chip Select Access Time
Chip Select Low to Output in Low-Z
10
12
15
20
____
____
____
____
(1)
4
4
5
5
CLZ
t
____
____
____
____
(1)
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
CHZ
t
____
____
____
____
OE
t
5
6
7
8
____
____
____
____
(1)
0
0
0
0
OLZ
t
____
____
____
____
(1)
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
ns
OHZ
t
OH
t
4
—
4
—
4
—
4
—
____
BE
t
—
5
—
6
—
7
8
____
____
____
____
(1)
0
0
0
0
BLZ
t
____
____
____
____
(1)
Byte Enable High to Output in High-Z
5
6
6
8
ns
BHZ
t
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
WC
t
Write Cycle Time
10
7
7
7
0
0
7
5
0
12
8
8
8
0
0
8
6
0
15
10
10
10
0
20
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AW
t
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
CW
t
BW
t
AS
t
WR
t
Address Hold from End of Write
Write Pulse Width
0
0
WP
t
10
7
12
9
DW
t
Data Valid to End of Write
Data Hold Time
DH
t
0
0
____
____
____
____
(1)
Write Enable High to Output in Low-Z
3
3
3
3
OW
t
____
____
____
____
(1)
Write Enable Low to Output in High-Z
5
6
6
8
ns
WHZ
t
5326 tbl 10
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 00C to +700C temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
5326 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Deviceiscontinuouslyselected,CSisLOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC
ADDRESS
tAA
tOH
OE
(3)
tOHZ
tOE
(3)
tOLZ
CS
(2)
tACS
(3)
(3)
tCHZ
tCLZ
BLE
BHE,
(2)
(3)
tBE
tBHZ
(3)
tBLZ
DATAOUT
DATA OUTVALID
5326 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. AddressmustbevalidpriortoorcoincidentwiththelaterofCS,BHE,orBLE transitionLOW;otherwisetAA isthelimitingparameter.
3. Transitionismeasured±200mVfromsteadystate.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
(2)
(5)
(5)
tCW
tCHZ
tBHZ
tBW
BHE , BLE
WE
tWR
tWP
tAS
(5)
tWHZ
(5)
tOW
tDH
(3)
DATAOUT
PREVIOUS DATA VALID
DATA VALID
tDW
DATAIN
DATAIN VALID
5326 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuouslyHIGH. IfduringaWE controlledwrite cycleOEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
6
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
(2)
tAS
tCW
tBW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
5326 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
(2)
tCW
tAS
tBW
BHE, BLE
tWP
tWR
WE
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
5326 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OEis continuouslyHIGH. IfduringaWE controlledwrite cycleOEis LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOEis HIGHduringaWEcontrolledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. IftheCSLOWorBHEandBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
7
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71T016
SA
XX
XXX
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Y
400-mil SOJ (SO44-1)
PH
BF
400-mil TSOP Type II (SO44-2)
7.0 x 7.0 mm FBGA (BF48-1)
10 **
12
15
Speed in nanoseconds
20
** C om m ercia l te m perature range only.
5326 drw 11
6.42
8
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
08/23/01
Creatednewdatasheet
CORPORATE HEADQUARTERS
2975 Stender Way
for SALES:
for Tech Support:
800-345-7015 or 408-727-6116 sramhelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com
800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
9
相关型号：
©2020 ICPDF网 联系我们和版权申明