74ALVCH162373PVG [IDT]
3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH;
| 型号： | 74ALVCH162373PVG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH |
| 文件： | 总6页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANS-
PARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
This16-bittransparentD-typelatchisbuiltusingadvanceddualmetalCMOS
technology.TheALVCH162373isparticularlysuitableforimple-mentingbuffer
registers,I/Oports,bidirectionalbusdrivers,andworkingregisters.Thisdevice
canbeusedastwo8-bitlatchesorone16-bitlatch.Whenthelatchenable(LE)
inputishigh,theQoutputsfollowthedata(D)inputs.WhenLEistakenlow,the
QoutputsarelatchedatthelevelssetupattheDinputs.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
Abufferedoutput-enable(OE)canbeusedtoplacetheeightoutputsineither
anormallogicstate(highorlowlogiclevels)orahigh-impedancestate.Inthe
high-impedancestate,theoutputsneitherloadnordrivethebuslinessignifi-
cantly.Thehigh-impedancestateandtheincreaseddriveprovidethecapability
todrivebuslineswithoutneedforinterfaceorpullupcomponents.OEdoesnot
affectinternaloperationsofthelatch.Olddatacanberetainedornewdatacan
beeneteredwhiletheoutputsareinthehigh-impedancestate.
TheALVCH162373hasseriesresistorsinthedeviceoutputstructurewhich
willsignificantlyreducelinenoisewhenusedwithlightloads. Thisdriverhas
beendesignedtodrive±12mAatthedesignatedthresholdlevels.
The ALVCH162373 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputsand
eliminatestheneedforpull-up/downresistor.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
1
24
2OE
1OE
48
47
25
36
2
LE
1
LE
C1
1D
C1
1D
2
13
1Q1
2Q1
1D1
2D1
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2016
1
© 2016 Integrated Device Technology, Inc.
DSC-4575/7
IDT74ALVCH162373
3.3VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1
LE
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
OE
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
1
Q1
1
D1
2
2
1Q2
3
1D
Continuous Clamp Current,
VI < 0 or VI > VCC
4
GND
GND
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
1
D3
1
Q
3
4
5
ICC
ISS
Continuous Current through each
VCC or GND
±100
1D
4
1
Q
6
NOTES:
V
CC
7
V
CC
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1
D5
1
Q5
8
1
D6
1
Q6
9
2. VCC terminals.
3. All terminals except VCC.
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
Q7
1
D7
1D
8
1
Q
8
1
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
2
D1
2
Q
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
2
D2
2Q2
COUT
CI/O
GND
GND
2Q3
2
D
3
4
NOTE:
1. As applicable to the device type.
2
D
2Q4
32
31
V
CC
V
CC
PINDESCRIPTION
2
D5
2Q5
30
29
28
27
26
Pin Names
xDx
Description
DataInputs(1)
2
D6
2Q6
xLE
LatchEnableInputs
3-StateOutputs
GND
GND
xQx
2
D7
2Q7
xOE
3-StateOutputEnableInput(ActiveLOW)
2
D8
2Q8
NOTE:
2
LE
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2OE
25
(1)
FUNCTION TABLE (EACH 8-BIT SECTION)
SSOP/ TSSOP
TOP VIEW
Inputs
Outputs
xOE
xLE
H
xDx
H
xQx
H
L
L
H
L
L
H
L
X
X
Z
(2)
L
X
Qo
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCH162373
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
5
5
μA
μA
μA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
10
—
10
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
–1.2
V
Input Hysteresis
—
—
100
0.1
—
40
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
μA
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
μA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
μA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
μA
μA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH162373
3.3VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
1.9
1.7
2.2
2
—
—
—
—
2.4
2
—
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
19
4
22
5
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
PropagationDelay
xDx to xQx
1.5
5.3
1.5
4.5
1.5
4
ns
ns
ns
ns
tPHL
tPLH
PropagationDelay
xLE to xQx
2
5.6
6.5
5.6
2
5
2
4
5
tPHL
tPZH
tPZL
OutputEnableTime
xOE to xQx
1.5
1.5
1.5
1.5
6
1.5
1.5
tPHZ
tPLZ
OutputDisableTime
xOE to xQx
5.5
4.5
tSU
SetupTime,databeforeLE↓
HoldTime,dataafterLE↓
Pulse Duration, LE HIGH or LOW
OutputSkew(2)
2
—
—
—
—
2
—
—
—
—
2
—
—
ns
ns
ns
ps
tH
1.5
3.3
—
1.5
3.3
—
1.5
3.3
—
tW
—
tSK(O)
NOTES:
500
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH162373
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
V
V
0V
IH
T
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
t
PHL
t
PLH
V
V
V
OH
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
T
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
OL
t
PHL
tPLH
VT
Vcc / 2
150
V
V
V
IH
T
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
0V
150
ALVC Link
30
Propagation Delay
V
LOAD
VCC
Open
GND
DISABLE
ENABLE
V
V
IH
T
500Ω
CONTROL
INPUT
VIN
VOUT
Pulse(1, 2)
Generator
0V
D.U.T.
tPZL
tPLZ
V
LOAD/2
V
LOAD/2
OUTPUT
NORMALLY
LOW
500Ω
SWITCH
CLOSED
VT
RT
V
V
OL + VLZ
OL
CL
t
PHZ
tPZH
OUTPUT
NORMALLY
HIGH
ALVC Link
V
OH
SWITCH
OPEN
Test Circuit for All Outputs
V
0V
T
VOH -
VHZ
0V
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
ALVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
V
IH
DATA
INPUT
V
T
SWITCHPOSITION
0V
tSU
t
H
V
IH
V
Test
Switch
VLOAD
GND
TIMING
INPUT
T
Open Drain
Disable Low
Enable Low
0V
tREM
V
IH
V
ASYNCHRONOUS
CONTROL
T
0V
Disable High
Enable High
V
IH
SYNCHRONOUS
CONTROL
V
T
tSU
0V
All Other Tests
Open
tH
ALVC Link
Set-up, Hold, and Release Times
V
V
IH
T
INPUT
0V
tPLH1
tPHL1
LOW-HIGH-LOW
V
V
V
OH
V
T
PULSE
T
OUTPUT 1
OL
t
W
tSK (x)
tSK (x)
V
V
V
OH
HIGH-LOW-HIGH
PULSE
V
T
T
ALVC Link
OUTPUT 2
OL
Pulse Width
tPLH2
tPHL2
t
SK(x) = tPLH2
-
t
PLH1 or
t
PHL2
-
t
PHL1
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH162373
3.3VCMOS16-BITTRANSPARENTD-TYPELATCHWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
X
XX
XXX
X
XX
ALVC
Device Type Package
Bus-Hold Family
Temp. Range
Blank
8
Tube
Tape and Reel
PVG
PAG
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
16-Bit Transparent D-Type Latch with 3-State Outputs
Double-Density with Resistors, 12mA
373
162
H
Bus-Hold
– 40°C to +85°C
74
DATASHEETDOCUMENTHISTORY
06/15/2016
Pg.
6
Updated the ordering information by adding Tape and Reel.
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6
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