74ALVCH32501BF [IDT]

CABGA-114, Tray;


型号：	74ALVCH32501BF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	CABGA-114, Tray 逻辑集成电路触发器
文件：	总8页 (文件大小：111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

3.3V CMOS 36-BIT

IDT74ALVCH32501

UNIVERSAL BUS TRANS-

CEIVER WITH 3-STATE

OUTPUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

This 36-bituniversalbus transceiveris builtusingadvanceddualmetal

CMOStechnology.TheALVCH32501combinesD-typelatchesandDtype

flip-flopstoallowdataflowintransparentlatchedandclockedmodes.Data

flow in each direction is controlled by output-enable (OEAB and OEBA),

latchenable(LEABandLEBA),andclock(CLKABandCLKBA)inputs.For

A-to-Bdata flow, the device operates intransparentmode whenLEABis

high. WhenLEABis low, the Adata is latchedifCLKABis heldata HIGH

or low logic level. If LEAB is low, the A bus data is stored in the latch/ flip-

flop on the low-to-high transition of CLKAB. OEAB performs the output

enable functiononthe Bport.Data flowfromBporttoAportis similarbut

requires using OEBA, LEBA and CLKBA. Flow-through organization of

signal pins simplifies layout. All inputs are designed with hysteresis for

improvednoise margin.

This ALVCH32501has beendesignedwitha±24mAoutputdriver.This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

The ALVCH32501 has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs

andeliminates the needforpull-up/downresistors.

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• VCC = 2.5V ± 0.2V

• CMOS power levels (0.4μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in 114-ball LFBGA package

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for Heavy Loads

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONALBLOCKDIAGRAM

1OEAB

2OEAB

1CLKBA

2CLKBA

1LEBA

2LEBA

1OEBA

2OEBA

1CLKAB

2CLKAB

1LEAB

2LEAB

1B1

2B1

1A1

2A1

TO 17 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

DECEMBER 2002

DSC-4764/4

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

PIN CONFIGURATION

1B15

1B16

GND

1A16

1B17

1B18

2B15

1B14

1B2

1B1

1B10

1B9

1B12

1B11

2B2

2B1

2B4

2B6

2B8

2B7

2B10

2B9

1B6

1B5

2B12

2B11

VCC

2A11

2B14

2B13

GND

2B17

2B18

GND

1B4

1B3

1B8

1B7

2CLKAB

1B13

VCC

1A13

2B3

2B5

VCC

2A5

2B16

GND

1CLKAB GND

VCC GND GND

1CLKBA GND

1OEBA 1LEBA

1A18 2LEAB

GND GND

2CLKBA

1OEAB GND

1LEAB

1A1

VCC GND

GND

2OEAB

2A1

GND

2A3

2LEBA

2A18

2OEBA

2A16

GND

2A13

1A3

1A5

1A7

1A11

2A9

1A9

2A7

1A15

1A17

2A8

2A10

2A12

2A14

2A17

1A2

1A4

1A10

1A14

2A2

2A6

2A15

1A8

1A12

1A6

2A4

LFBGA

TOPVIEW

114 BALL LFBGA PACKAGE ATTRIBUTES

1.5mm Max.

1.4mm Nom.

1.3mm Min.

0.8mm

TOP VIEW

5.5mm

16mm

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol

Description

Max

Unit

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

(2)

VTERM

Terminal Voltage with Respect to GND

–0.5 to +4.6

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC+0.5

COUT

CI/O

TSTG

IOUT

IIK

Storage Temperature

DC Output Current

–65 to +150

–50 to +50

±50

° C

NOTE:

Continuous Clamp Current,

VI < 0 or VI > VCC

1. As applicable to the device type.

IOK

Continuous Clamp Current, VO < 0

–50

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. V^CCterminals.

3. All terminals except VCC.

(1,2)

FUNCTION TABLE (EACH FLIP-FLOP)

PINDESCRIPTION

Inputs

Outputs

Pin Names

OEAB

OEBA

Description

A-to-BOutputEnableInput

OEAB

LEAB

CLKAB

xAx

xBx

B-to-AOutputEnable Input(Active LOW)

A-to-BLatchEnableInput

↑

LEAB

LEBA

B-to-ALatchEnableInput

CLKAB

CLKBA

xAx

A-to-B Clock Input

B-to-A Clock Input

A-to-BDataInputsorB-to-A3-StateOutputs⁽¹⁾

↑

(3)

(4)

xBx

B-to-ADataInputsorA-to-B3-StateOutputs⁽¹⁾

NOTES:

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High Impedance

↑ = LOW-to-HIGH Transition

2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and

CLKBA.

3. Output level before the indicated steady-state conditions were established.

4. Output level before the indicated steady-state conditions were established, provided

that CLKAB was HIGH before LEAB went LOW.

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

Input HIGH Current

VCC = 3.6V

VI = VCC

—

µA

µ A

Input LOW Current

VI = GND

VO = VCC

VO = GND

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

—

Clamp Diode Voltage

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

–0.7

–1.2

Input Hysteresis

—

100

0.1

—

µ A

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

—

750

µ A

NOTE:

1. Typical values are at VCC = 3.3V, +25°C ambient.

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

–45

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

VCC = 2.3V

VCC = 2.7V

VCC = 3V

—

1.7

—

2.2

—

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, TA = 25°C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Symbol

CPD

Parameter

Test Conditions

Typical

108

Unit

PowerDissipationCapacitanceOutputsenabled

PowerDissipationCapacitanceOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

PropagationDelay

xCLK to xQx

5.3

—

4.9

4.2

tPHL

tPLH

tPHL

PropagationDelay

4.8

5.7

—

4.5

5.3

3.9

4.6

xAx to xBx or xBx to xAx

tPLH

tPHL

PropagationDelay

LE to xAx or xBx

1.1

1.3

tPLH

tPHL

tPZH

tPZL

tPZH

tPZL

tPHZ

PropagationDelay

CLK to Ax or Bx

OutputEnableTime

OEBA to xAx

1.2

1.3

6.1

6.3

5.8

5.3

—

5.6

1.4

1.1

4.9

OutputEnableTime

OEAB to xBx

5.3

4.6

4.2

OutputDisableTime

1.3

tPLZ

tPHZ

tPLZ

tSU

OEBA to xAx

OutputDisableTime

1.5

6.2

—

5.7

1.4

OEAB to xBx

Set-upTime,databeforeCLK↑

HoldTime,dataafterCLK↑

Set-upTime,databeforeLE↓

2.2

0.6

1.9

1.3

1.4

3.3

—

2.1

0.6

1.6

1.1

1.7

3.3

—

1.7

0.7

1.5

—

tSU

CLK HIGH

CLK LOW

Hold Time, data after LE↓, CLK HIGH or LOW

1.4

3.3

Pulse Width,LE HIGH

Pulse Width, CLK HIGH or LOW

3.3

—

3.3

—

3.3

—

(2)

tSK(o)

OutputSkew

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

(1)

(2)

Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit

tPHL

tPLH

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

Vcc / 2

150

VIH

OPPOSITE PHASE

INPUT TRANSITION

VLZ

VHZ

150

ALVC Link

Propagation Delay

VLOAD

Open

GND

DISABLE

VCC

ENABLE

VIH

CONTROL

INPUT

500Ω

tPZL

tPLZ

VIN

VOUT

(1, 2)

Pulse

VLOAD/2

D.U.T.

VLOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

Generator

V^LZ

VOL

CLOSED

500Ω

tPHZ

tPZH

OUTPUT

NORMALLY

HIGH

VOH

VHZ

SWITCH

OPEN

ALVC Link

Test Circuit for All Outputs

ALVC Link

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

NOTES:

VIH

1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.

DATA

INPUT

t^SU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

Open

tREM

Open Drain

Disable Low

Enable Low

VIH

ASYNCHRONOUS

CONTROL

VIH

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

All Other Tests

ALVC Link

VIH

Set-up, Hold, and Release Times

INPUT

tPLH1

t^PHL1

V^OH

VOL

LOW-HIGH-LOW

PULSE

OUTPUT 1

tSK (x)

VOH

VOL

HIGH-LOW-HIGH

PULSE

OUTPUT 2

ALVC Link

tPLH2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

tPHL2

Pulse Width

ALVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH32501

3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

XXXX

IDT

ALVC

Device Type Package

Bus-Hold

Family

Temp. Range

Low-Profile Fine Pitch Ball Grid Array

LFBGA - Green

BFG

36-Bit Universal Bus Transceiver

with 3-State Outputs

501

32-Bit Bus Density, 24mA

Bus-Hold

-40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

74ALVCH32501BF [IDT]

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