74FCT162511CTPAG8 [IDT]
TSSOP-56, Reel;
| 型号： | 74FCT162511CTPAG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-56, Reel |
| 文件： | 总10页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS 16-BIT
IDT54/74FCT162511AT/CT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
The FCT162511T 16-bit registered/latched transceiver with parity is built
usingadvanceddualmetalCMOStechnology. This high-speed, low-power
transceivercombinesD-typelatchesandD-typeflip-flopstoallowdataflowin
transparent, latched, or clocked modes. The device has a parity generator/
checkerintheA-to-BdirectionandaparitycheckerintheB-to-Adirection. Error
checkingisdoneatthebytelevelwithseparateparitybitsforeachbyte. Separate
errorflagsexitsforeachdirectionwithasingleerrorflagindicatinganerrorfor
eitherbyteintheA-to-Bdirectionandaseconderrorflagindicatinganerrorfor
eitherbyteintheB-to-Adirection. Theparityerrorflagsareopendrainoutputs
whichcanbetiedtogetherand/ortiedwithflagsfromotherdevicestoformasingle
errorflagorinterrupt. The parityerrorflags are enabledbythe OExx control
pins allowing the designer to disable the error flag during combinational
transitions.
Thecontrolpins LEAB,CLKAB,andOEAB controloperationintheA-to-B
directionwhileLEBA,CLKBA,andOEBAcontroltheB-to-Adirection. GEN/
CHKisonlyfortheselectionofA-to-Boperation. TheB-to-Adirectionisalways
incheckingmode. TheODD/EVENselectiscommonbetweenthetwodirections.
Except for the ODD/EVEN control, independent operation can be achieved
betweenthetwodirectionsbyusingthecorrespondingcontrollines.
• Typical tsk(o) (Output Skew) < 250ps, clocked mode
• Low input and output leakage ≤1µA (max)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 5V ±10%
• Balanced Output Drivers:
– ±24mA(industrial)
– ±16mA(military)
• Series current limiting resistors
• Generate/Check, Check/Check modes
• Open drain parity error allows wire-OR
• Available in the following packages:
– Industrial: SSOP, TSSOP
– Military: CERPACK
FUNCTIONALBLOCKDIAGRAM
LEAB
CLKAB
Data
OEAB
Parity, data
B0-15
16
18
PB1,2
Parity
Latch/
Register
GEN/CHK
Byte
2
Parity
PERB
Generator/
Checker
A0-15
PA1,2
(Open Drain)
ODD/EVEN
LEBA
CLKBA
Parity, Data
18
Parity, data
18
Latch/
Register
OEBA
Byte
Parity
Checking
PERA
(Open Drain)
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2009
1
© 2009 Integrated Device Technology, Inc.
DSC-2916/4
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
BLOCKDIAGRAM
ODD/EVEN
OEAB
LEBA
CLKBA
CLKAB
LEAB
C
C
D
B0
- B7
D
A0 - A7
C
D
C
D
OEBA
P
C
D
C
D
O
I
PB
1
PA
1
P
C
D
C
D
C
D
C
D
B8 - B15
A8 - A15
C
D
C
D
P
C
D
C
D
O
I
PB
2
PA
2
C
D
C
D
C
D
C
D
PERB
(Open Drain)
GEN/CHK
C
D
C
D
PERA
(Open Drain)
P
2
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to 7
OEAB
LEAB
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GEN/CHK
CLKAB
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
PA
1
3
PB
1
NOTES:
GND
4
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
A
0
1
5
B
B
V
B
B
B
B
B
B
0
A
6
1
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
VCC
7
CC
2
A2
A3
A4
A5
A6
A7
8
9
3
CAPACITANCE (TA = +25°C, F = 1.0MHz)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
4
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 0V
Typ.
3.5
Max. Unit
5
6
8
6
pF
pF
pF
CI/O
VOUT = 0V
VOUT = 0V
3.5
6
CO
Open Drain
Capacitance
3.5
7
GND
PERB
GND
PERA
PINDESCRIPTION
A
8
9
B
B
B
B
B
B
V
B
B
8
Pin Names
OEAB
OEBA
LEAB
Description
A
9
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-BLatchEnableInput
A10
A11
A12
A13
10
11
12
13
CC
14
15
LEBA
B-to-ALatchEnableInput
CLKAB
CLKBA
Ax
A-to-B Clock Input
B-to-A Clock Input
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-BParityInput, B-to-AParityOutput
B-to-AParityInput, A-to-BParityOutput
ParityModeSelectionInput
VCC
Bx
A14
PERA
PERB
PAx(1)
A15
GND
PA
GND
PB
PBx
2
2
ODD/EVEN
GEN/CHK
CLKBA
OEBA
LEBA
AtoBPort Generate or Check Mode Input
ODD/EVEN
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
SSOP/ TSSOP/ CERPACK
TOP VIEW
3
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
FUNCTIONTABLE(1, 4)
FUNCTIONTABLE
(PARITY CHECKING) (1, 2, 3, 4)
Inputs
Outputs
(5)
OEAB
LEAB
X
CLKAB
Ax
X
L
Bx
Z
A0 – A7 and PA1
H
L
L
L
L
L
L
X
X
X
↑
Number of inputs that are high
1, 3, 5, 7 or 9
ODD/EVEN
PERB
H
L
L
H
L
L
(6)
H
H
L
H
L
1, 3, 5, 7 or 9
H
(6)
L
0, 2, 4, 6 or 8
H
L
↑
H
X
X
H
0, 2, 4, 6 or 8
H
L
(2)
L
L
B
NOTES:
(3)
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB
= H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the
corresponding data regardless of parity errors (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered
clock.
5. Conditions shown are for the byte A0–A7 and PA1. The byte A8–A15 and PA2 is similiar.
6. The parity error flag PERB is a combined flag for both bytes A0–A7 and A8–A15. If a parity
error occurs on either byte PERB will go low. PERB is an open drain output which must
be externally pulled up to achieve a logic HIGH.
L
H
B
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
and CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
FUNCTIONTABLE
(PARITY GENERATION) (1, 2, 3, 4, 5)
A0 – A7
Number of inputs that are high
ODD/EVEN
PB1
1, 3, 5 or 7
L
H
L
H
1, 3, 5 or 7
L
0, 2, 4, 6 or 8
L
0, 2, 4, 6 or 8
H
H
NOTES:
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B
is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge
triggered clock.
4. Conditions shown are for the byte A–A7. The byte A8–A15 is similiar but will output
the parity on PB2.
5. The error flag PERB will remain in a high state during parity generation.
4
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Min.
2
Typ.(2)
—
Max.
—
0.8
1
Unit
V
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
–80
—
V
IIH
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
VI = VCC
—
µA
—
1
IIL
VI = GND
—
1
—
1
IOZH
IOZL
VIK
IOS
VCC = Max.
VO = 2.7V
VO = 0.5V
—
1
µA
(5)
(3-State Output pins)
—
1
Clamp Diode Voltage
Short Circuit Current
VCC = Min., IIN = –18mA
–0.7
–140
–1.2
–250
V
(3)
VCC = Max., VO = GND
mA
VH
Input Hysteresis
—
—
—
100
5
—
mV
µ A
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
500
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
mA
mA
mA
µ A
(3)
IODL
Output LOW
Current
(I/O pins)
VCC = 5V, VIN = VIH or VIL, VO = 1.5V
60
—
–60
—
115
250
–115
—
200
—
(OpenDrain)
(3)
IODH
IOFF
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VO = 1.5V
–200
±1
OutputPowerOffLeakageCurrent
(OpenDrain)(5)
VCC = 0, VO ≤ 5.5V
VOH
VOL
Output HIGH Voltage (I/O pins)
VCC = Min.
IOH = –16mA MIL
IOH = –24mA IND
IOL = 16mA MIL
IOL = 24mA IND
IOL = 48mA MIL
IOL = 64mA IND
2.4
—
—
3.3
0.3
0.3
—
V
V
V
VIN = VIH or VIL
VCC = Min.
OutputLOW
Voltage
(I/O pins)
(OpenDrain)
0.55
0.55
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = –55°C.
5
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
All other Input Pins
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
ΔICC
VCC = Max.
mA
(3)
VIN = 3.4V
Parity Input Pins (PAx, PBx)
—
1
2.5
ICCD
IC
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OEAB = GND, OEBA = VCC
One Input Togging
VIN = VCC
VIN = GND
—
75
120
µ A /
MHz
50% Duty Cycle
Total Power Supply Current(6)
VCC = Max.
VIN = VCC
—
0.8
1.7
mA
Outputs Open
VIN = GND
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = GND, OEBA = VCC
LEAB = GND
One Bit Toggling
fi = 5MHz
VIN = 3.4V
VIN = GND
—
—
1.3
3.8
3.2
50% Duty Cycle
VCC = Max.
VIN = VCC
6.5(5)
Outputs Open
VIN = GND
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = GND, OEBA = VCC
LEAB = GND
Eighteen Bits Toggling
fi = 2.5MHz
(5)
VIN = 3.4V
VIN = GND
—
9
21.8
50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
6
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
(PROPAGATIONDELAYS)
FCT162511AT
FCT162511CT
Max. Min.(2)
Ind.
Mil.
Ind.
Min.(2)
Mil.
Symbol
tPLH
Parameter
Condition(1) Min.(2)
Max.
Min.(2)
Max.
Max.
Unit
Propagation Delay, PAx to PBx
Ax to Bx or Bx to Ax, PBx to PAx
CL = 50pF
1.5
5
1.5
5.3
1.5
4.2
1.5
4.5
ns
tPHL
RL = 500Ω
tPLH
PropagationDelay
GEN/CHK LOW
1.5
7.5
1.5
8
1.5
6.5
1.5
6.8
ns
tPHL
Ax to PBx
(3)
tPLH
PropagationDelay
1.5
1.5
1.5
1.5
9
8
9
8
1.5
1.5
1.5
1.5
9
8
9
8
1.5
1.5
1.5
1.5
7.5
6.5
7.5
6.5
1.5
1.5
1.5
1.5
7.8
6.8
7.8
6.8
ns
ns
ns
ns
tPHL
Ax to PERB, PAx to PERB
PropagationDelay
(3)
tPLH
tPHL
tPLH
tPHL
Bx to PERA, PBx to PERA
PropagationDelay
LEBA to Ax and PAx
LEAB to Bx and PBx
PropagationDelay
1.5
5.6
1.5
6
1.5
5.3
1.5
5.5
ns
(3)
tPLH
1.5
1.5
7
6
1.5
1.5
7
6
1.5
1.5
6
5
1.5
1.5
6.3
5.3
ns
ns
tPHL
tPLH
tPHL
LEBA to PERA, LEAB to PERB
PropagationDelay
CLKBA to Ax and PAx
CLKAB to Bx and PBx
PropagationDelay
1.5
5.6
1.5
6
1.5
5.3
1.5
5.5
ns
(3)
tPLH
1.5
1.5
7
6
1.5
1.5
7
6
1.5
1.5
6
5
1.5
1.5
6.3
5.3
ns
ns
tPHL
CLKBA to PERA
CLKAB to PERB
tPZH
tPZL
OutputEnableTime
OEBA to Ax and PAx
OEAB to Bx and PBx
OutputDisableTime
1.5
1.5
6
1.5
1.5
6.5
6
1.5
1.5
5.6
5.2
1.5
1.5
5.8
5.5
ns
ns
tPHZ
tPLZ
OEBA to Ax and PAx
OEAB to Bx and PBx
Parity ERROR Enable
OEBA to PERA, OEAB to PERB
ODD/EVEN to PERx
5.6
(3)
tPLZ
1.5
1.5
1.5
1.5
1.5
6
6
1.5
1.5
1.5
1.5
1.5
6.3
6.3
10
1.5
1.5
1.5
1.5
1.5
6
6
1.5
1.5
1.5
1.5
1.5
6.3
6.3
10
ns
ns
ns
ns
ns
tPZL
(3)
tPLH
10
10
10
10
10
10
tPHL
10
10
tPLH
tPHL
ODD/EVEN to PBx
10
10
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. On Open Drain Outputs tPLH is measured at VOUT = VOL + 0.3V.
7
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)
FCT162511AT
Ind. Mil.
Min. Max. Min. Max. Min. Max. Min. Max. Unit
FCT162511CT
Ind. Mil.
Symbol
Parameter
Set-upTime
Test Conditions(1, 3)
PBx valid
tSU
GEN/CHK LOW
GEN/CHK HIGH
GEN/CHK HIGH
CL = 50pF
4
3
4
3
4
3
4
3
—
—
—
—
—
—
—
—
4
3
4
3
4
3
4
4
—
—
—
—
—
—
—
—
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
3.5
3
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
HIGH or LOW
Ax to CLKAB
PBx not valid
PERB valid
RL = 500Ω
3
PERB not valid
PERB valid
3
tSU
tSU
Set-upTime
3
PAx to CLKAB
Set-upTime
PERB not valid
PERA valid
3
3
Bx to CLKBA,
PBx to CLKBA
Set-upTime
PERA not valid
3
tSU
CLKAB LOW
PBx valid
3.5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
3.5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ax to LEAB
GEN/CHK LOW
CLKAB LOW
PBx not valid
PERB valid
3.5
3
3.5
3
GEN/CHK HIGH
CLKAB HIGH
GEN/CHK LOW
CLKAB HIGH
GEN/CHK HIGH
CLKAB LOW
PERB not valid
PBx valid
3.5
3
3.5
3
PBx not valid
PERB valid
3.5
3
3.5
3
PERB not valid
PERB valid
tSU
tSU
Set-upTime
3.5
3
3.5
3
PAx to LEAB
GEN/CHK HIGH
CLKAB HIGH
GEN/CHK HIGH
CLKBA LOW
PERB not valid
PERB valid
3.5
3
3.5
3
PERB not valid
PERA valid
Set-upTime
3.5
3
3.5
3
Bx to LEBA
PBx to LEBA
PERA not valid
PERA valid
CLKBA HIGH
3.5
3
3.5
3
PERA not valid
(4)
tSK(O)
OutputSkew
—
—
0.5 ns
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE(HOLDTIMES)
FCT162511AT
Ind. Mil.
Condition(1) Min. Max. Min. Max. Min. Max. Min. Max. Unit
FCT162511CT
Ind. Mil.
Symbol
Parameter
tH
tH
tH
tH
tH
tW
tW
Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA
Hold Time HIGH or LOW PAx to LEAB
Hold Time HIGH or LOW PBx to LEBA
Hold Time Ax to CLKAB, PAx to CLKAB
Hold Time Bx to CLKBA, PBx to CLKBA
CL= 50pF
1
1
1
1
1
3
3
—
—
—
—
—
—
—
1
1
1
1
1
3
3
—
—
—
—
—
—
—
1
1
1
0
0
3
3
—
—
—
—
—
—
—
1
1
1
0
0
3
3
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
RL = 500Ω
(2)
LEAB or LEBA Pulse Width HIGH
(2)
CLKAB or CLKBA Pulse Width HIGH or LOW
NOTES:
1. See test circuits and waveforms.
2. This parameter is guaranteed but not tested.
3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the
A to B or B to A port respective to the indicated direction.
4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/
latched mode. This parameter is guaranteed by design.
8
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
SWITCHPOSITION
TESTCIRCUITSANDWAVEFORMS
Test
Switch
Closed
Open
Open Drain
Disable Low
Enable Low
V
CC
7.0V
500Ω
500Ω
All Other Tests
V
OUT
V
IN
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Pulse
Generator
D.U.T.
50pF
RT
CL
Test Circuits for All Outputs
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
t
W
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL
tPLH
t
0.3V
0.3V
VOL
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
9
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
XX
FCT
XXXX
XXX
XX
X
Temp. Range
Family
Package
Process
Device Type
Blank
B
Industrial
MIL-STD-883, Class B
Industrial Options
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
PVG
PAG
Military Options
CERPACK
E
18-Bit Registered/Latched Transceiver
511AT
511CT
162
Double-Density, 5 Volt, Balanced Drive
54
74
55 C to +125 C
40 C to +85 C
DatasheetDocumentHistory
09/06/09 Pg.6
Updatedthe orderinginformationbyremovingthe "IDT"notationandnonRoHSpart.
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logichelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
10
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