83948AYI-147 [IDT]
Low Skew Clock Driver, 83948 Series, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026ABC-HD, LQFP-32;
| 型号： | 83948AYI-147 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 83948 Series, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026ABC-HD, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总17页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-12 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
ICS83948I-147
General Description
Features
The ICS83948I-147 is a low skew, 1-to-12 Differential-to-LVC-
MOS/LVTTL Fanout Buffer. The ICS83948I-147 has two select-
able clock inputs. The CLK, nCLK pair can accept most standard
differential input levels. The LVCMOS_CLK can accept LVCMOS
or LVTTL input levels. The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50 series or parallel terminated trans-
mission lines. The effective fanout can be increased from 12 to 24
by utilizing the ability of the outputs to drive two series terminated
lines.
• Twelve LVCMOS/LVTTL outputs
• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock
input
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
• Output frequency: 350MHz
• Additive phase jitter, RMS: 0.14ps (typical)
• Output skew: 100ps (maximum), 3.3V 5ꢀ
• Part-to-part skew: 1ns (maximum), 3.3V 5ꢀ
• Operating supply modes:
The ICS83948I-147 is characterized at full 3.3V, full 2.5V or mixed
3.3V core/2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83948I-147 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
CLK_EN
D
Q
32 31 30 29 28 27 26 25
LVCMOS_CLK
1
1
2
3
4
5
6
7
8
CLK_SEL
GND
24
23
22
21
20
Q0
CLK
nCLK
LVCMOS_CLK
CLK
Q4
0
Q1
VDDO
Q5
CLK_SEL
nCLK
Q2
CLK_EN
GND
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
OE
VDD
Q6
19
18
17
VDDO
Q7
GND
9
10 11 12 13 14 15 16
ICS83948I-147
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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Table 1. Pin Descriptions
Number
Name
Type
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
1
CLK_SEL
Input
Pullup
2
3
4
5
LVCMOS_CLK
CLK
Input
Input
Input
Input
Pullup
Pullup
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
nCLK
Pulldown Inverting differential clock input.
CLK_EN
Pullup
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, outputs are in an High-impedance state.
when HIGH, outputs are active. LVCMOS/LVTTL interface levels.
6
OE
VDD
GND
Input
Power
Power
Pullup
7
Power supply pin.
8, 12, 16,
20, 24, 28, 32
Power supply ground.
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 18,
22, 26, 30
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
k
k
Power Dissipation Capacitance
(per output)
CPD
12
7
pF
ROUT
Output Impedance
5
12
Function Tables
Table 3A. Clock Select Function Table
Control
Input
Clock
0
1
CLK/nCLK inputs selected
LVCMOS_CLK input selected
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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Table 3B. Clock Input Function Table
Inputs
Outputs
Q[0:11]
LOW
CLK_SEL LVCMOS_CLK
CLK
nCLK
Input to Output Mode
Polarity
0
0
0
0
0
0
1
1
–
–
–
–
–
–
0
1
0
1
0
1
1
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
0
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
–
–
Biased; NOTE 1
Inverting
–
–
LOW
Non-Inverting
Non-Inverting
HIGH
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
73.6C/W (0 mps)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
55
Units
V
VDD
VDDO
IDD
Power Supply Voltage
Output Supply Voltage
Power Supply Current
3.135
3.3
V
mA
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
52
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
2.375
2.5
V
mA
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Table 4C. Power Supply DC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Power Supply Voltage
3.465
2.625
55
V
V
Output Supply Voltage
Power Supply Current
2.375
2.5
mA
Table 4D. DC Characteristics, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DD = 3.465V
VDD = 2.625V
Minimum
Typical
Maximum Units
LVCMOS
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
Input High Voltage
LVCMOS
LVCMOS
LVCMOS
1.7
-0.3
-0.3
V
V
DD = 3.465V
DD = 2.625V
V
VIL
IIN
Input Low Voltage
Input Current
0.7
V
VIN = VDD or VIN = 3.465V or 2.625V
300
µA
V
DDO = 3.3V 5ꢀ
IOH = -24mA
2.4
1.8
V
V
V
V
V
V
VOH
Output High Voltage; NOTE 1
VDDO = 2.5V 5ꢀ
IOH = -15mA
VDDO = 3.3V 5ꢀ
IOL = 24mA
0.55
0.30
0.6
VDDO = 3.3V 5ꢀ
IOL = 12mA
VOL
Output Low Voltage; NOTE 1
Peak-to-Peak Input
VDDO = 2.5V 5ꢀ
IOL = 15mA
VPP
CLK/nCLK
VDD = 3.465V or 2.625V
VDD = 3.465V or 2.625V
0.15
1.3
Voltage; NOTE 2
Common Mode
Input Voltage;
NOTE 2, 3
CLK/nCLK
VCMR
GND + 0.5
VDD – 0.85
V
NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2.
See Parameter Measurement section, Output Load AC Test Circuit diagrams.
NOTE 2: VIL should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as VIH.
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C to 85°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
4
MHz
ns
CLK/nCLK; NOTE 1
ƒ 350MHz
ƒ 350MHz
2
2
tPD
Propagation Delay
LVCMOS_CLK;
NOTE 2
4
ns
155.52MHz,
Integration Range:
12kHz – 20MHz
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
tjit
0.14
1
ps
Measured on the Rising Edge
@ VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
1
ps
ns
Measured on the Rising Edge
@ VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
0.8V to 2V
0.2
45
1.0
55
5
ns
ꢀ
Output Duty Cycle
ƒ 150MHz, Ref = CLK/nCLK
50
tPZL, PZH
t
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
ns
tPLZ, PHZ
t
5
CLK_EN to CLK/nCLK
1
0
0
1
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
ns
ns
ns
CLK/nCLK to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
LVCMOS_CLK to
CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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Table 5B. AC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
4.2
MHz
ns
CLK/nCLK; NOTE 1
ƒ 350MHz
ƒ 350MHz
1.5
1.7
tPD
Propagation Delay
LVCMOS_CLK;
NOTE 2
4.4
ns
155.52MHz,
Integration Range:
12kHz – 20MHz
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
tjit
0.14
1
ps
Measured on the Rising Edge
@ VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
160
2
ps
ns
Measured on the Rising Edge
@ VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
0.6V to 1.8V
0.1
40
1.0
60
5
ns
ꢀ
Output Duty Cycle
ƒ 150MHz, Ref = CLK/nCLK
tPZL, PZH
t
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
ns
tPLZ, PHZ
t
5
CLK_EN to CLK/nCLK
1
0
0
1
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
ns
ns
ns
CLK/nCLK to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
LVCMOS_CLK to
CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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Table 5C. AC Characteristics, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C to 85°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
4
MHz
ns
CLK/nCLK; NOTE 1
ƒ 350MHz
ƒ 350MHz
2
2
tPD
Propagation Delay
LVCMOS_CLK;
NOTE 2
4
ns
155.52MHz,
Integration Range:
12kHz – 20MHz
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
tjit
0.14
1
ps
Measured on the Rising Edge
@ VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
1
ps
ns
Measured on the Rising Edge
@ VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
0.8V to 2V
0.1
45
1.0
55
5
ns
ꢀ
Output Duty Cycle
ƒ 200MHz, Ref = CLK/nCLK
tPZL, PZH
t
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
ns
tPLZ, PHZ
t
5
CLK_EN to CLK/nCLK
1
0
0
1
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
ns
ns
ns
CLK/nCLK to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
LVCMOS_CLK to
CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz (12kHz to 20MHz) =
0.14ps (typical)
Offset From Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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Parameter Measurement Information
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
V
DD,
V
DD,
V
V
DDO
DDO
Qx
Qx
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
2.05V 5ꢀ
1.25V 5ꢀ
V
DD
SCOPE
V
DD
nCLK
VPP
VCMR
Cross Points
V
DDO
Qx
CLK
GND
GND
-1.25V 5ꢀ
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
Differential Input Level
Part 1
VDDO
VDDO
Qx
Qy
2
Qx
Qy
2
Part 2
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
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Parameter Measurement Information, continued
1.8V
tF
2V
1.8V
tR
2V
0.6V
0.6V
0.8V
0.8V
Q0:Q11
Q0:Q11
tR
tF
3.3V Output Rise/Fall Time
2.5V Output Rise/Fall Time
VDD
2
CLK
VDDO
2
Q0:Q11
nCLK
CLK
tPW
tPERIOD
tPW
x 100ꢀ
odc =
VDDO
2
tPERIOD
Q0:Q11
➤
tPD
➤
Output Duty Cycle/Pulse Width/Period
Propagation Delay
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Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to
ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example, in Figure
2A, the input termination applies for IDT open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50Ω
R2
50Ω
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
R2
84Ω
84Ω
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
*R3
*R4
33Ω
33Ω
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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ICS83948AYI-147 REV. D NOVEMBER 1, 2012
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LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Reliability Information
Table 6. JA vs. Air Flow Table for a 32 Lead LQFP
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
73.6°C/W
63.9°C/W
60.3°C/W
Transistor Count
The transistor count for ICS83948I-147 is: 1040
Pin compatible with the MPC9448
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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ICS83948AYI-147 REV. D NOVEMBER 1, 2012
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LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Package Outline and Package Dimension
Package Outline - Y Suffix for 32 Lead LQFP
Table 7. Package Dimensions for 32 Lead LQFP
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
D1 & E1
D2 & E2
e
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
L
0.45
0°
0.75
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
14
ICS83948AYI-147 REV. D NOVEMBER 1, 2012
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Ordering Information
Table 8. Ordering Information
Part/Order Number
83948AYI-147
83948AYI-147T
83948AYI-147LF
83948AYI-147ILFT
Marking
Package
32 Lead LQFP
32 Lead LQFP
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
ICS83948AI147
ICS83948AI147
ICS948AI147L
ICS948AI147L
Tape & Reel
Tray
Tape & Reel
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
15
ICS83948AYI-147 REV. D NOVEMBER 1, 2012
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LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
2
Features Section - added Lead-Free bullet.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical; and
T2
added 5 min. and 12 max to ROUT
.
B
11/21/05
7
Updated Single Ended Signal Driving Differential Input diagram.
Added Recommendations for Unused Input and Output Pins.
T8
10
Ordering Information Table - added lead-free part number, marking, and note.
1
5
6
Features Section - added Additive Phase Jitter bullet.
3.3V AC Characteristics Table - added Additive Phase Jitter.
3.3V AC Characteristics Table - added Additive Phase Jitter.
Added Additive Phase Jitter section.
T5A
T5B
C
7
1/15/08
11
12
Updated Differential Input Clock Interface section.
Updated Reliability Information.
T6
Updated format throughout the datasheet.
1
4
7
9
Features Section - added mix voltage to supply voltage bullet.
Added Mix DC Characteristics Power Supply Table.
Added Mix AC Characteristics Table.
Parameter Measurement Information Section - added 3.3V/2.5V LVCMOS
Output Load AC Test Circuit diagram.
T4C
T5C
D
D
4/1/09
T8
T1
15
2
Ordering Information Table - deleted ICS prefix from Part/Order Number
column.
Output supply pins, Changed VDD to VDDO
11/1/12
IDT™ / ICS™ LVCMOS/LVTTL CLOCK GENERATOR
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ICS83948AYI-147 REV. D NOVEMBER 1, 2012
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
We’ve Got Your Timing Solution
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
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相关型号：
83948AYI-147T
Low Skew Clock Driver, 83948 Series, 12 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026ABC-HD, LQFP-32
IDT
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