843034-06_技术文档

FemtoClock™ Multi-Rate 3.3V LVPECL

Frequency Synthesizer

843034-06

DATA SHEET

GENERAL DESCRIPTION

FEATURES

The 843034-06 is a general purpose, low phase noise LVPECL

synthesizer which can generate frequencies for a wide variety of

applications.The 843034-06 has a 4:1 input multiplexer from which

the following inputs can be selected: one differential input, one

single-ended input, or one of two crystal oscillators, thus making

the device ideal for frequency translation or frequency generation.

The 843034-06 has dual LVPECL outputs that may be programmed

for ÷2, ÷4 or ÷5 of theVCO frequency.The 843034-06 also supplies

a buffered copy of the reference clock or crystal frequency on the

single-ended REF_OUT pin which can be enabled or disabled

(disabled by default). The output frequency can be programmed

using either a serial or parallel programming interface. This device

supports Spread Spectrum Clocking (SSC) for EMI reduction.

• Dual differential 3.3V LVPECL outputs

• 4:1 Input Mux:

One differential input

One single-ended input

Two crystal oscillator interfaces

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Output frequency range: 120MHz to 375MHz

• Crystal input frequency range: 12MHz to 40MHz

• VCO range: 600MHz to 750MHz

• Supports Spread Spectrum Clocking (SSC)

• Parallel or serial interface for programming feedback divider

and output dividers

• RMS phase jitter at 166.6MHz, using a 22.222MHz crystal

(12kHz to 30MHz): 1.33ps (typical), SSC - Off

• 3.3V supply mode

• 0°C to 75°C ambient operating temperature

• Available in lead-free (RoHS 6) package

BLOCK DIAGRAM

Pullup

OE_A

÷

001

011

100

2

4

5

Pullup

VCO_SEL

XTAL_IN0

FOUTA0

nFOUTA0

PIN ASSIGNMENT

00

01

OSC

XTAL_OUT0

XTAL_IN1

0

1

V_{CCO_A}

XTAL_OUT1

Phase

Detector

VCO

Pullup

CLK

nCLK

V_{CCO_B}

10

11

Pullup/Pulldown

FOUTB0

nFOUTB0

Pulldown

REF_CLK

÷M

Pulldown

SEL1

SEL0

Pullup

OE_B

MR

V_{CCO_REF}

REF_OUT

Pulldown

OE_REF

S_LOAD

TEST

S_DATA

S_CLOCK

Configuration

Interface

Logic

nP_LOAD

M8:M0

M0:M4 M6:M8 Pulldown, M5 Pullup

NA2 Pulldown, NA1:0 Pullup

NA2:NA0

843034-06 REVISION B 8/17/15

1

843034-06 DATA SHEET

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes operation

using a 22.22MHz crystal. Valid PLL loop divider values for differ-

ent crystal or input frequencies are deﬁned in the Input Frequency

Characteristics, Table 6, NOTE 1.

will automatically occur during power-up. The TEST output is

LOW when operating in the parallel input mode. The relationship

between theVCO frequency, the crystal frequency and the M divider

is deﬁned as follows: fVCO = fxtal x M

The 843034-06 features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A fundamental crystal is used as the input to the on-

chip oscillator. The output of the oscillator is fed into the phase

detector. A 22.22MHz crystal provides a 22.22MHz phase detector

reference frequency.The VCO of the PLL operates over a range of

600MHz to 750MHz. The output of the M divider is also applied to

the phase detector.

The M value and the required values of M0 through M8 are shown

in Table 4B to program the VCO Frequency Function Table.Valid M

values for which the PLL will achieve lock for a 22.22MHz reference

are deﬁned as 26 ≤ M ≤ 33.The frequency out is deﬁned as follows:

FOUT = fVCO = fxtal x M

N

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW.The shift register is loaded by sampling the S_DATA bits with

the rising edge of S_CLOCK. The contents of the shift register are

loaded into the M divider and NA output divider when S_LOAD tran-

sitions from LOW-to-HIGH.The M divide and NA output divide values

are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD

is held HIGH, data at the S_DATA input is passed directly to the M

divider and NA output divider on each rising edge of S_CLOCK.

The serial mode can be used to program the M and NA bits and

test bits T1 and T0.The internal registers T0 and T1 determine the

state of the TEST output as follows:

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting the

VCO control voltage.Note that for some values of M (either too high

or too low), the PLL will not achieve lock. The output of the VCO is

scaled by a divider prior to being sent to each of the LVPECL output

buffers. The divider provides a 50% output duty cycle.

The 843034-06 supports either serial or parallel programming

modes to program the M feedback divider and N output divider.

Figure 1 shows the timing diagram for each mode. In parallel

mode, the nP_LOAD input is initially LOW. The data on the M

and NA inputs are passed directly to the M divider and N output

dividers. On the LOW-to-HIGH transition of the nP_LOAD input,

the data is latched and the M and N dividers remain loaded until

the next LOW transition on nP_LOAD or until a serial event oc-

curs. As a result, the M and NA bits can be hardwired to set the

M divider and NA output divider to a speciﬁc default state that

T1 T0

TEST Output

LOW

0

1

0

1

0

1

S_Data, Shift Register Output

Output of M divider

Same frequency as FOUTA0

FemtoClock™ Multi-Rate 3.3V LVPECL

Frequency Synthesizer

2

REVISION B 8/17/15

843034-06 DATA SHEET

TABLE 1. SSM OPERATION

SS Bit Pattern

Operation

SS3

0

SS2

0

SS1

0

SS0

0

Mode

%

off

0

1

center

off

0.25

0.85

1.45

1.7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

down

-0.25

-0.75

-1.25

-1.5

1

0

1

0

1

0

1

0

1

0

1

0

1

NOTE: SS modulation frequency is approximately 32kHz using

reference frequency of 22.22MHz, providing a VCO frequency of

666.66MHz.

SPREAD SPECTRUM MODULATION

The 843034-06 offers the option of a spread spectrum modulated

output clock. The spread spectrum is controlled via 4 bits in the

serial bit stream. These four bits conﬁgure the SSM to be enabled

and the amount of spread modulation to be selected. See Table

1 for the deﬁnition of the four bits. The four bits are added at the

beginning of the serial data stream and are labeled SS3, SS2, SS1

and SS0. The initial state of SS3, SS2, SS1 and SS0 is 0, 0, 0, 0

which places the 843034-06 in the mode of spread spectrum off.

Additionally, a parallel load will result in spread spectrum modulation

being off.The 843034-06 offers down-spread or center-spread using

triangle-wave modulation. NOTE:PLL operation not guaranteed for

M >31 when using center spread.

POWER-UP OPERATION

MR PIN OPERATION

The 843034-06 has internal power–up reset circuitry that initiates

the phase lock loop to automatically acquire lock on power-up. On

power-up the M/N values for the feedback and output dividers will be

acquired from the M and N pins if nP_Load is held Low. If nP_Load

is High during power-up, M/N values are indeterminate. The M/N

values may be changed by either changing the values on the M/N

pins when nP_LOAD is low or with a serial load when nP_LOAD is

high and S_LOAD is low.

Any time there is a change in the input frequency, either due to an

external change or a change in the SEL pins, the MR pin must go

high and low to relock to the new input frequency. A change in the

M feedback divider by either a serial or parallel load will also cause

a relock to the new input frequency.

REVISION B 8/17/15

3

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

TABLE 2. PIN DESCRIPTIONS

Number

Name

Type

Description

1, 41, 42,

43, 44, 45,

47, 48

M8, M0, M1,

M2, M3,

M4, M6, M7

M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD

input. LVCMOS/LVTTL interface levels.

Input

Pulldown

2, 3, 4

RESERVED

Reserve

Input

Reserved pins. Do not connect.

Output enable. Controls enabling and disabling of REF_OUT output.

LVCMOS/LVTTL interface levels.

5

OE_REF

Pulldown

Pullup

Output enable. Controls enabling and disabling of FOUTA0, nFOUTA0

outputs. LVCMOS/LVTTL interface levels.

6

7

OE_A

OE_B

Input

Output enable. Controls enabling and disabling of FOUTB0, nFOUTB0

outputs. LVCMOS/LVTTL interface levels.

Pullup

8, 14

9, 10

11

V

Power

Input

Core supply pins.

CC

NA0, NA1

NA2

Pullup

Determines output divider value as deﬁned in Table 4C,

Function Table. LVCMOS/LVTTL interface levels.

Input

Pulldown

12, 24

V

Power

Negative supply pins.

EE

Test output which is ACTIVE in the serial mode of operation.

Output driven LOW in parallel mode.

13

TEST

Output

LVCMOS/LVTTL interface levels.

FOUTA0, nFOU-

TA0

15, 16

17

Output

Power

Output

Differential output for the synthesizer. LVPECL interface levels.

Output supply pin for FOUTA0, nFOUTA0.

V

CCO_A

FOUTB0,

nFOUTB0

18, 19

Differential output for the synthesizer. LVPECL interface levels.

20

21

22

23

V

Power

Output

Power

Output supply pin for FOUTB0, nFOUTB0.

Reference clock output. LVCMOS/LVTTL interface levels.

Output supply pin for REF_OUT output.

No connect.

CCO_B

REF_OUT

V

CCO_REF

nc

Unused

Active High Master Reset. When logic HIGH, forces the internal PLL to

a reset condition which holds the VCO at the minumum value. When

25

MR

Input

Pulldown logic LOW, the internal dividers and the outputs are enabled. Assertion

of MR does not affect loaded M, N, S and T values. LVCMOS/LVTTL

interface levels.

Clocks in serial data present at S_DATA input into the shift register on

the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.

26

27

28

S_CLOCK

S_DATA

Input

Pulldown

Shift register serial input. Data sampled on the rising edge

of S_CLOCK. LVCMOS/LVTTL interface levels.

Pulldown

Controls transition of data from shift register into the dividers. LVC-

MOS/LVTTL interface levels.

S_LOAD

Pulldown

29

30, 31

32

V

Power

Input

Analog supply pin.

CCA

SEL0, SEL1

REF_CLK

Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.

Pulldown Reference clock input. LVCMOS/LVTTL interface levels.

XTAL_IN0,

XTAL_OUT0

Crystal oscillator interface. XTAL_IN0 is the input,

XTAL_OUT0 is the output.

33, 34

35, 36

Input

XTAL_IN1,

XTAL_OUT1

Crystal oscillator interface. XTAL_IN1 is the input,

XTAL_OUT1 is the output.

Continued on next page...

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

4

REVISION B 8/17/15

843034-06 DATA SHEET

TABLE 2. PIN DESCRIPTIONS, CONTINUED

Number

Name

Type

Description

37

CLK

Input Pulldown Non-inverting differential clock input.

Pullup/

38

nCLK

Input

Inverting differential clock input.V /2 default when left ﬂoating.

CC

Pulldown

Parallel load input. Determines when data present at M8:M0 is loaded into

39

nP_LOAD

Input Pulldown M divider, and when data present at NA2:NA0 is loaded into the N output

dividers. LVCMOS/LVTTL interface levels.

Determines whether synthesizer is in PLL or bypass mode.

LVCMOS/LVTTL interface levels.

40

46

VCO_SEL

M5

Input

Pullup

M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input.

LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.

TABLE 3. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

C

R

Input Capacitance

4

51

7

pF

kΩ

Ω

IN

Input Pullup Resistor

PULLUP

PULLDOWN

OUT

Input Pulldown Resistor

Output Impedance

REF_OUT

5

12

REVISION B 8/17/15

5

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE

Inputs

Conditions

MR nP_LOAD

M

N

S_LOAD S_CLOCK S_DATA

H

X

Reset the PLL.

Data on M and N inputs passed directly to the M divider

and N output divider. TEST output forced LOW.

L

Data Data

X

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

L

↑

H

L

↑

X

↑

L

X

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

X

Data

Contents of the shift register are passed to the

M divider and N output divider.

L

H

X

↓

L

X

↑

Data

X

M divider and N output divider values are latched.

Parallel or serial input do not affect shift registers.

S_DATA passed directly to M divider as it is clocked.

H

Data

NOTE: L = LOW

H = HIGH

X = Don’t care

↑ = Rising edge transition

↓ = Falling edge transition

TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE

256

M8

0

128

M7

0

64

M6

0

32

M5

0

16

M4

1

8

M3

1

4

M2

0

2

M1

1

M0

0

VCO Frequency

(MHz)

M Divide

600

27

•

666.6

30

•

0

1

0

•

711.04 (default)

733.3

32

33

0

1

0

1

0

1

NOTE 1: These M divide values and the resulting frequencies correspond to crystal, CLK, or REF_CLK input frequency of

22.22MHz.

TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE

Inputs

Output Frequency (MHz)

N Divider Value

*NA2

*NA1

*NA0

Minimum

300

Maximum

375

0

1

0

1

0

1

0

2

4

5

150

187.5 (default)

150

120

*NOTE: Programming for Bank A and Bank B.

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

6

REVISION B 8/17/15

843034-06 DATA SHEET

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

4.6V

CC

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁcations only. Functional

operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Inputs, V

-0.5V to V + 0.5V

I

CC

Outputs, V (LVCMOS)

-0.5V to V + 0.5V

O

CCO

Outputs, I (LVPECL)

O

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, θ

65.7°C/W (0 mps)

-65°C to 150°C

JA

Storage Temperature, T

STG

TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, V = V

= V

= 3.3V 5%, V = 0V, TA = 0°C TO 75°C

CCO_REF EE

CC

CCO_A

CCO_B

Symbol Parameter

Test Conditions

Minimum

Typical

3.3

Maximum Units

V

Core Supply Voltage

3.135

3.465

V

CC

Analog Supply Voltage

V – 0.17

3.3

V

CCA

CC

V^CCO_A,

Output Supply Voltage

3.135

3.3

3.465

V

V^CCO_B,

CCO_REF

I

Power Supply Current

Analog Supply Current

173

17

mA

EE

I

CCA

TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, V = V

= 3.3V 5%, V = 0V, TA = 0°C TO 75°C

EE

CC

CCO_REF

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V

Input High Voltage

Input Low Voltage

REF_CLK, MR,

2

V

+ 0.3

V

IH

CC

-0.3

0.8

IL

SEL[1:0], OE_REF,

S_CLOCK, S_DATA,

S_LOAD, nP_LOAD,

NA2, M1:M4, M6:M8

V

= V = 3.465V

150

5

µA

CC

IN

Input

High Current

I

IH

OE_A, M5, OE_B,

VCO_SEL, NA0, NA1

= V = 3.465V

CC

IN

REF_CLK, MR,

SEL[1:0], OE_REF,

S_CLOCK, S_DATA,

S_LOAD, nP_LOAD,

NA2, M1:M4, M6:M8

V

= 3.465V,

CC

-5

V = 0V

Input

Low Current

IN

I

IL

OE_A, M5, OE_B,

VCO_SEL, NA0, NA1

V

= 3.465V,

CC

-150

2.6

V = 0V

IN

TEST; NOTE 1

REF_OUT

V

Output

High Voltage

V

= 3.3V 5%

OH

OL

CCO_REF

V

- 0.3V

CCO_REF

TEST; NOTE 1

REF_OUT

0.5

0.4

Output

Low Voltage

V

= 3.3V 5%

CCO_REF

NOTE 1: Outputs terminated with 50Ω to V

Circuit Diagrams.

/2. See Parameter Measurement Information Section, “Output Load Test

CCO_REF

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

REVISION B 8/17/15

7

843034-06 DATA SHEET

TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, V = V

= V

= 3.3V 5%, V = 0V, TA = 0°C TO 75°C

CC

CCO_A

CCO_B EE

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

nCLK

V = V = 3.465V

150

µA

V

IN

CC

I

Input High Current

Input Low Current

IH

CLK

nCLK

CLK

V = V = 3.465V

IN CC

V = 0V, V = 3.465V

-150

-5

IN

CC

I

IL

V = 0V, V = 3.465V

IN

CC

V

Peak-to-Peak Input Voltage; NOTE 1

0.15

1.3

PP

Common Mode Input Voltage; NOTE 1, 2

V

+ 0.5

V - 0.85

CC

V

CMR

EE

NOTE 1: V should not be less than -0.3V.

IL

NOTE 2: Common mode voltage is deﬁned as V .

IH

TABLE 5D. LVPECL DC CHARACTERISTICS, V = V

= V

= 3.3V 5%, V = 0V, TA = 0°C TO 75°C

CCO_B EE

CC

CCO_A

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

V

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

V

- 1.4

- 2.0

V

- 0.9

- 1.7

V

OH

CCO

V

OL

CCO

V

0.6

1.0

SWING

NOTE 1: Outputs terminated with 50Ω to V

V

- 2V.

CCO_A,

CCO_B

TABLE 6. INPUT FREQUENCY CHARACTERISTICS, V = V

= V

= 3.3V 5%, V = 0V, TA = 0°C TO 75°C

CCO_REF EE

CC

CCO_A

CCO_B

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

XTAL_IN0/XTAL_OUT0,

XTAL_IN1/XTAL_OUT1

12

40

MHz

f

Input Frequency

IN

CLK/nCLK, REF_CLK

S_CLOCK

40

50

MHz

NOTE: For the input crystal, CLK/nCLK and REF_CLK frequency range, the M value must be set for the VCO to operate with-

in the 600MHz to 750MHz range. Using the minimum input frequency of 12MHz, valid values of M are 50 ≤ M ≤ 62. Using the

maximum frequency of 40MHz, valid values of M are 15 ≤ M ≤ 18.

TABLE 7. CRYSTAL CHARACTERISTICS

Parameter

Test Conditions

Minimum Typical Maximum

Units

Mode of Oscillation

Frequency

Fundamental

12

40

50

7

MHz

Ω

Equivalent Series Resistance (ESR)

Shunt Capacitance

pF

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

8

REVISION B 8/17/15

843034-06 DATA SHEET

TABLE 8. AC CHARACTERISTICS, V = V

= V

= 3.3V 5%, V = 0V, TA = 0°C TO 75°C

EE

CCO_REF

CC

CCO_A

CCO_B

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

FOUT

Output Frequency

120

375

MHz

166.6MHz,

Integration Range:

12kHz - 30MHz

Phase Jitter, RMS (Random), SSC-Off

NOTE 1, 2

tjit(Ø)

1.33

ps

tjit(cc)

tsk(o)

Cycle-to-Cycle Jitter; NOTE 2, 3, 4

Output Skew; NOTE 2, 4, 5

35

ps

120

Output

tR / tF

LVPECL Outputs

Rise/Fall Time

20% to 80%

200

700

ps

M, N to nP_LOAD

5

ns

%

tS

Setup Time

Hold Time

S_DATA to S_CLOCK

S_CLOCK to S_LOAD

M, N to nP_LOAD

5

tH

S_DATA to S_CLOCK

S_CLOCK to S_LOAD

5

N = 4 or N = 5

N = 2

48

45

52

55

odc

Output Duty Cycle

PLL Lock Time

%

tLOCK

100

ms

NOTE: Electrical parameters are guaranteed over the speciﬁed ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airﬂow greater than 500 lfpm. The device will meet

speciﬁcations after thermal equilibrium has been reached under these conditons.“

NOTE: Characterized using a 22.22MHz crystal producing a VCO frequency of 666.66MHz, unless otherwise noted.

NOTE: See Parameter Measurement Information section.

NOTE 1: Please refer to the Phase Noise Plot.

NOTE 2: Characterized with REF_OUT output disabled.

NOTE 3: Jitter performance using XTAL inputs.

NOTE 4: This parameter is deﬁned in accordance with JEDEC Standard 65.

NOTE 5: Deﬁned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

REVISION B 8/17/15

9

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

TYPICAL PHASE NOISE AT 166.6MHZ

Filter

166.6MHz

RMS Phase Jitter (Random)

12kHz to 30MHz = 1.33ps (typical)

Raw Phase Noise Data

Phase Noise Result by adding

a Filter to raw data

OFFSET FREQUENCY (HZ)

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

10

REVISION B 8/17/15

843034-06 DATA SHEET

PARAMETER MEASUREMENT INFORMATION

3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVELS

OUTPUT SKEW

CYCLE-TO-CYCLE JITTER

OUTPUT RISE/FALL TIME

OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

11

REVISION B 8/17/15

843034-06 DATA SHEET

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The 843034-06

provides separate power supplies to isolate any high switching noise

from the outputs to the internal PLL. V , V and V should be

CC

CCA

CCO_X

individually connected to the power supply plane through vias, and

0.01µF bypass capacitors should be used for each pin. Figure 2

illustrates this for a genericV pin and also shows thatV requires

CC

CCA

that an additional10Ω resistor along with a 10µF bypass capacitor

be connected to the V pin.

CCA

FIGURE 2. POWER SUPPLY FILTERING

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS

Figure 3 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V /2 is

generated by the bias resistors R1, R2 and C1. This bias ^Cc^Circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/

CC

R1 = 0.609.

FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

REVISION B 8/17/15

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FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both V^SWINGand VOH must meet the VPP and

Please consult with the vendor of the driver component to conﬁrm

the driver termination requirements. For example in Figure 4A, the

input termination applies for IDT HiPerClockS open emitter LVHSTL

drivers. If you are using an LVHSTL driver from another vendor,

use their termination recommendation.

V

CMR input requirements. Figures 4A to 4F show interface examples

for the HiPerClockS CLK/nCLK input driven by the most common

driver types.The input interfaces suggested here are examples only.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

Input

LVPECL

nCLK

HiPerClockS

Input

LVHSTL

R1

50

R2

50

ICS

R1

50

R2

50

HiPerClockS

LVHSTL Driver

R3

50

FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY AN IDT OPEN EMITTER

FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVPECL DRIVER

HIPERCLOCKS LVHSTL DRIVER

3.3V

Zo = 50 Ohm

R3

125

R4

125

Zo = 50 Ohm

LVDS_Driver

CLK

R1

100

nCLK

Receiver

HiPerClockS

Input

LVPECL

Zo = 50 Ohm

R1

84

R2

84

FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT

FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V LVDS DRIVER

DRIVEN BY A 3.3V LVPECL DRIVER

FIGURE 4F. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 2.5V SSTL DRIVER

FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT

DRIVEN BY A 3.3V HCSL DRIVER

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

13

REVISION B 8/17/15

843034-06 DATA SHEET

CRYSTAL INPUT INTERFACE

The 843034-06 has been characterized with 18pF parallel resonant

crystals.The capacitor values, C1 and C2, shown in Figure 5 below

were determined using a 18pF parallel resonant crystal and were

chosen to minimize the ppm error.The optimum C1 and C2 values

can be slightly adjusted for different board layouts.

XTAL_IN

C1

27pF

X1

18pF Parallel Crystal

XTAL_OUT

C2

27pF

FIGURE 5. CRYSTAL INPUt INTERFACE

LVCMOS TO XTAL INTERFACE

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 6. The XTAL_OUT pin can be left ﬂoating. The

input edge rate can be as slow as 10ns. For LVCMOS signals, it

is recommended that the amplitude be reduced from full swing to

half swing in order to prevent signal interference with the power

rail and to reduce noise.This conﬁguration requires that the output

impedance of the driver (Ro) plus the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination

at the crystal input will attenuate the signal in half.This can be done

in one of two ways. First, R1 and R2 in parallel should equal the

transmission line impedance. For most 50Ω applications, R1 and

R2 can be 100Ω. This can also be accomplished by removing R1

and making R2 50Ω.

VDD

R1

.1uf

Ro

Rs

Zo = 50

XTAL_IN

R2

Zo = Ro + Rs

XTAL_OU T

FIGURE 6. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

REVISION B 8/17/15

14

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

CRYSTAL INPUTS

LVCMOS OUTPUTS

For applications not requiring the use of the crystal oscillator input,

both XTAL_IN and XTAL_OUT can be left ﬂoating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from XTAL_IN to ground.

The unused LVCMOS output can be left ﬂoating. We recommend

that there is no trace attached.

LVPECL O^UTPUTS

All unused LVPECL outputs can be left ﬂoating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left ﬂoating or terminated.

CLK/nCLK I^NPUTS

For applications not requiring the use of the differential input, both

CLK and nCLK can be left ﬂoating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

REF_CLK I^NPUT

For applications not requiring the use of the reference clock, it can

be left ﬂoating.Though not required, but for additional protection, a

1kΩ resistor can be tied from the REF_CLK to ground.

LVCMOS C^ONTROLPINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are recom-

mended only as guidelines.

to maximize operating frequency and minimize signal distortion.

Figures 7A and 7B show two different layouts which are recom-

mended only as guidelines. Other suitable clock layouts may exist

and it would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock com-

ponent process variations.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50Ω

transmission lines.Matched impedance techniques should be used

3.3V

R3

R4

125

3.3V

Z

_o= 50

+

_

Input

Z_o= 50

R1

84

R2

84

FIGURE 7A. LVPECL OUTPUT TERMINATION

FIGURE 7B. LVPECL OUTPUT TERMINATION

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

15

REVISION B 8/17/15

843034-06 DATA SHEET

APPLICATION SCHEMATIC EXAMPLE

board layout, the C1 and C2 may be slightly adjusted for

optimizing frequency accuracy. For the LVPECL output

drivers, only two termination examples are shown in this

schematic. Additional termination approaches are shown in

the LVPECL Termination Application Note.

Figure 8 shows an example of 843034-06 application

schematic. In this example, the device is operated at

V =V = 3.3V. The device are be driven by a crystal,

CC

LVCM^CO^COS or LVPECL input sources. The 18pF parallel

resonant 25MHz crystal is used. The C1 = 27pF and C2 =

27pF are recommended for frequency accuracy.For different

VCC

3.3V

R1

133

R2

133

Zo = 50 Ohm

3.3V

LVPECL

Driver_LVPECL

R3

133

R4

133

R5

82.5

R6

82.5

Zo = 50 Ohm

FOUTA0

C1

27pF

25MHzX1

18pF

+

-

nFOUTA0

C2

27pF

U1

R7

82.5

R8

82.5

VCC

R9

VCC

10

M8

1

36

35

34

33

32

31

30

29

28

27

26

25

VCCA

C3

M8

XTAL_OUT1

XTAL_IN1

XTAL_OUT0

XTAL_IN0

REF_CLK

SEL1

2

3

RESERVED

OE_REF

OE_A

C4

4

VCC=3.3V

VCCO=3.3V

0.01u

OE_REF

OE_A

OE_B

VCC

NA0

NA1

NA2

5

10u

SEL1

SEL0

6

VCC

7

OE_B

VCC

NA0

NA1

NA2

VEE

SEL0

8

VCCA

9

S_LOAD

S_DATA

S_CLOCK

MR

10

11

12

C5

0.1u

MR

Zo = 50 Ohm

FOUTB0

+

-

nFOUTB0

Logic Control Input Examples

VCC

R10

50

R11

50

VCCO

Set Logic

Input to

'1'

Set Logic

Input to

'0'

RU2

Not Install

VCC

C6

0.1u

C7

0.1u

R12

50

Optional

Y-Termination

RU1

1K

VCCO

To Logic

Input

pins

To Logic

Input

pins

VCCO

C8

0.1u

RD1

RD2

1K

Not Install

C9

0.1u

R13

33

Zo = 50 Ohm

REF_OUT

LVCMOS

F^IGURE8. 843034-06 APPLICATION SCHEMATIC EXAMPLE

REVISION B 8/17/15

16

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the 843034-06.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 843034-06 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.

CC

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

Core and LVPECL Output Power Dissipation

•

Power (core) = V

* I

= 3.465V * 173mA = 599.45mW

EE_MAX

MAX

CC_MAX

Power (outputs) = 30mW/Loaded Output pair

MAX

If all outputs are loaded, the total power is 2 * 30mW = 60mW

LVCMOS Output Power Dissipation

•

Output Impedance R Power Dissipation due to Loading 50Ω to V

/2

OUT

CCO_REF

Output Current I = V

/ [2 * (50Ω + R )] = 3.465V / [2 * (50Ω + 7Ω] = 30.4mA

OUT

CCO_MAX

OUT

Power Dissipation on the R per LVCMOS output

OUT

2

Power (R ) = R * (I ) = 7Ω * (30.4mA) = 6.97mW per output

OUT

Total Power Dissipation

Total Power

•

= Power (LVPECL) + Power (R

)

OUT

= 599.45mW + 60mW + 6.47mW

= 665.92mW

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

17

REVISION B 8/17/15

843034-06 DATA SHEET

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of

the device. The maximum recommended junction temperature for devices is 125°C.

The equation for Tj is as follows: Tj = θ^JA* Pd_total + T

A

Tj = Junction Temperature

θ

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

= Ambient Temperature

T

A

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ^JAmust be used. Assuming no air ﬂow

and a multi-layer board, the appropriate value is 65.7°C/W per Table 9 below.

Therefore, Tj for an ambient temperature of 75°C with all outputs switching is:

75°C + 0.666W * 65.7°C/W = 118°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air ﬂow,

and the type of board (single layer or multi-layer).

TABLE 9. THERMAL RESISTANCE θ_JAFOR 48-PIN LQFP, FORCED CONVECTION

θ_JAby Velocity (Meters per Second)

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

65.7°C/W

55.9°C/W

52.4°C/W

REVISION B 8/17/15

18

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 9.

FIGURE 9. LVPECL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V – 2V.

CCO

•

For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX}– 0.9V

)

(V_{CCO_MAX}– V_{OH_MAX}= 0.9V

For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX}– 1.7V

)

(V_{CCO_MAX}– V_{OL_MAX}= 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

))

Pd_H = [(V_{OH_MAX}– (V_{CCO_MAX}– 2V))/R ] * (V_{CCO_MAX}– V_{OH_MAX}) = [(2V – (V_{CCO_MAX}– V_{OH_MAX}/R ] * (V_{CCO_MAX}– V_{OH_MAX}) =

L

[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW

))

Pd_L = [(V_{OL_MAX}– (V_{CCO_MAX}– 2V))/R ] * (V_{CCO_MAX}– V_{OL_MAX}) = [(2V – (V_{CCO_MAX}– V_{OL_MAX}/R ] * (V_{CCO_MAX}– V_{OL_MAX}) =

L

[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

19

REVISION B 8/17/15

843034-06 DATA SHEET

RELIABILITY INFORMATION

TABLE 10. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP

JA

θ_JAby Velocity (Meters per Second)

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

65.7°C/W

55.9°C/W

52.4°C/W

TRANSISTOR COUNT

The transistor count for 843034-06 is: 7846

REVISION B 8/17/15

20

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

PACKAGE OUTLINE -Y SUFFIX FOR 48 LEAD LQFP

T^ABLE11. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBC

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

48

--

1.60

0.15

1.45

0.27

0.20

A1

A2

b

0.05

1.35

0.17

0.09

1.40

0.22

c

--

D

9.00 BASIC

7.00 BASIC

5.50 Ref.

9.00 BASIC

7.00 BASIC

5.50 Ref.

0.50 BASIC

0.60

D1

D2

E

E1

E2

e

L

0.45

0°

0.75

7°

--

θ

ccc

--

0.08

Reference Document: JEDEC Publication 95, MS-026

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

21

REVISION B 8/17/15

843034-06 DATA SHEET

TABLE 12. ORDERING INFORMATION

Part/Order Number

843034EY-06LF

Marking

Package

Shipping Packaging

tray

Temperature

ICS43034E06L

48 Lead “Lead-Free” LQFP

0°C to 75°C

843034EY-06LFT

tape & reel

NOTE: Parts that are ordered with an “LF” sufﬁx to the part number are the Pb-Free conﬁguration and are RoHS compliant.

REVISION B 8/17/15

22

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

843034-06 DATA SHEET

REVISION HISTORY SHEET

Description of Change

Rev

Table

Page

Date

A

8

16

Added Applications Schematic.

11/19/08

1

6

8

9

Features Section - changed min. VCO from 560MHz to 600MHz.

Programmable VCO Frequency Table - changed ﬁrst row VCO frequency from

577.7 to 600 and M Divide from 26 to 27.

Programmable Output Divider Table - change Output Frequency Minimum columns from

(1st row) 280 to 300; (2nd row) 140 to 150; (3rd row) 112 to 120.

Input Frequency Characteristics - changed VCO min. from 560MHz to 600MHz. Change

min. input frequency value from 47 to 50, changed max. value from 14 to 15.

AC Characteristics Table - changed min. output frequency from 112MHz to 120MHz.

T4B

T4C

T6

B

8/10/09

8/17/15

T8

Product Discontinuation Notice - Last time buy expires August 14, 2016.

PDN CQ-15-04

Updated data sheet format.

FemtoClock™ Multi-Rate 3.3V LVPECL Frequency Synthesizer

23

REVISION B 8/17/15

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, California 95138

Sales

800-345-7015 or +408-284-8200

Fax: 408-284-2775

www.IDT.com

Technical Support

email: clocks@idt.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or speciﬁcations described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance speciﬁcations and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth-

er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.

This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason-

ably expected to signiﬁcantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or

their respective third party owners.


型号：	843034-06
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FemtoClockâ¢ Multi-Rate 3.3V LVPECL Frequency Synthesizer
文件：	总24页 (文件大小：538K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

843034-06 [IDT]

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