8432CK-51LFT [IDT]
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER;
| 型号： | 8432CK-51LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总21页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
ICS8432-51
GENERAL DESCRIPTION
FEATURES
The ICS8432-51 is a general purpose, dual output Crystal-to-
3.3V Differential LVPECL High Frequency Synthesizer. The
ICS8432-51 has a selectable REF_CLK or crystal input. The
VCO operates at a frequency range of 250MHz to 700MHz. The
VCO frequency is programmed in steps equal to the value of
the input reference or crystal frequency. The VCO and output
frequency can be programmed using the serial or parallel inter-
face to the configuration logic. The low phase noise character-
istics of the ICS8432-51 make it an ideal clock source for Giga-
bit Ethernet, Fibre Channel 1 and 2, and Infiniband applica-
tions.
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
• Output frequency range: 31.25MHz to 700MHz
• Crystal input frequency range: 12MHz to 25MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter and
output dividers
• RMS period jitter: 3.5ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Replaces the ICS8432-01
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
VCO_SEL
XTAL_SEL
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
REF_CLK
XTAL_SEL
VCCA
REF_CLK
0
XTAL1
1
OSC
ICS8432-51
S_LOAD
S_DATA
S_CLOCK
MR
XTAL2
VEE
PLL
9
10 11 12 13 14 15 16
PHASE DETECTOR
÷1
MR
0
1
VCO
÷2
÷4
÷8
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ M
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
Top View
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
M0:M8
N0:N1
Top View
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for dif-
ferent crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
N output divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when operating
in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x M
The ICS8432-51 features a fully integrated PLL and therefore,
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscilla-
tor. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 10 ≤ M ≤ 28. The frequency out is de-
fined as follows: FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift reg-ister
are loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly
to the M divider and N output divider on each ris-ing edge of
S_CLOCK. The serial mode can be used to program the M and N
bits and test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-51 support two in-
put modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1 shows
the timing diagram for each mode. In parallel mode, the nP_LOAD
input is initially LOW. The data on inputs M0 through M8 and N0
and N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data
is latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. As a result,
the M and N bits can be hardwired to set the M divider and
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS Fout
S
ERIAL LOADING
S_CLOCK
S_DATA
T1
T0
*
NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
t
H
S
S_LOAD
nP_LOAD
t
S
P
ARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
M, N
t
t
S
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
9
TEST
Output
10
VCC
Power
Output
Power
Output
Core supply pin.
11, 12
13
FOUT1, nFOUT1
VCCO
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
14, 15
FOUT0, nFOUT0
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the
17
MR
Input
Pulldown inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
effect loaded M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
Pulldown
18
19
S_CLOCK
S_DATA
Input
Input
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
Pulldown
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
22
23
XTAL_SEL
REF_CLK
Input
Pullup
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
Input
Input
Pulldown Referenc clock input. LVCMOS / LVTTL interface levels.
24,
25
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
k
k
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
3
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
L
L
X
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
L
L
X
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
= Rising edge transition
= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Divide
250
275
•
10
11
•
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
0
N0
0
Minimum
Maximum
700
1
2
4
8
250
125
0
1
350
1
0
62.5
31.25
175
1
1
87.5
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
32 Lead LQFP
32 Lead VFQFN
JA
47.9°C/W (0 lfpm)
41.07°C/W (0 lfpm)
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
VCC –0.15
3.135
3.3
3.3
3.3
3.465
3.465
3.465
135
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
2
V
CC + 0.3
V
V
Input
VIH
High Voltage
REF_CLK
2
VCC + 0.3
0.8
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, N0:N1,
S_DATA, S_CLOCK, M0:M8
-0.3
-0.3
V
Input
VIL
Low Voltage
REF_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, REF_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
VCC = VIN = 3.465V
150
µA
Input
IIH
High Current
M5, XTAL_SEL, VCO_SEL
5
µA
µA
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, REF_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
V
CC = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
Output
VOH
High Voltage
Output
VOL
TEST; NOTE 1
0.5
V
Low Voltage
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
5
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V. See "Parameter Measurement Information" section,
figure "3.3V Output Load Test Circuit".
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK; NOTE 1
12
12
25
25
50
MHz
MHz
MHz
XTAL_IN, XTAL_OUT;
NOTE 1
fIN
Input Frequency
S_CLOCK
NOTE 1: For the input crystal and REF_CLK frequency range, the M value must be set for the VCO to operate within the
250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 M 58. Using the
maximum frequency of 25MHz, valid values of M are 10 M 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
25
70
7
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7. AC CHARACTERISTICS, VCC = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ps
FOUT
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1, 3
31.25
700
25
tjit(cc)
fVCO > 350MHz
tjit(per) Period Jitter, RMS; NOTE 1
3.5
15
ps
tsk(o)
Output Skew; NOTE 2, 3
Output Rise/Fall Time
ps
tR / tF
20% to 80%
200
700
ps
M, N to nP_LOAD
5
ns
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
M, N to nP_LOAD
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
48
ns
odc
tPW
Output Duty Cycle
Output Pulse Width
PLL Lock Time
N > 1
N = 1
52
%
tPERIOD/2 - 150
tPERIOD/2 + 150
1
ps
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
6
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2V
nFOUTx
SCOPE
VCC
VCCO
,
Qx
FOUTx
VCCA
nFOUTy
FOUTy
LVPECL
nQx
VEE
VEE
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH
nFOUTx
FOUTx
VREF
➤
➤
tcycle n+1
tcycle n+1
tcycle n
➤
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
tjit(cc) = tcycle n – tcycle n+1
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx
nFOUTx
80%
80%
FOUTx
VSWING
20%
tPW
tPERIOD
20%
FOUTx
tF
tR
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
7
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common
frequencies used as well as the settings for the ICS8432-51 to
generate the appropriate frequency.
Table 8. Common SANs Application Frequencies
Reference Frequency to SERDES
(MHz)
Crystal Frequency
(MHz)
Interconnect Technology
Gigabit Ethernet
Fibre Channel
Clock Rate
1.25 GHz
125, 250, 156.25
25, 19.53125
FC1 1.0625 GHz
FC2 2.1250 GHz
106.25, 53.125, 132.8125
125, 250
16.6015625, 25
25
Infiniband
2.5 GHz
Table 9. Configuration Details for SANs Applications
ICS8432-51
ICS8432-51
M & N Settings
Interconnect
Technology
Crystal Frequency
(MHz)
Output Frequency
to SERDES
(MHz)
M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0
25
125
250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
25
Gigabit Ethernet
25
156.25
156.25
53.125
106.25
132.8125
125
19.53125
25
Fiber Channel 1
Fiber Channel 2
Infiniband
25
16.6015625
25
25
250
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS8432-51 pro-
vides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA and VCCO should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin.
Figure 2 illustrates this for a generic VCC pin and also shows that
VCCA requires that an additional 10Ω resistor along with a 10µF
bypass capacitor be connected to the VCCA pin.
3.3V
VCC
.01µF
10Ω
VCCA
.01µF
10 µF
FIGURE 2. POWER SUPPLY FILTERING
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
8
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS8432-51 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 3 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
FIGURE 3. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
9
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
LVPECL OUTPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_CLK INPUT
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the REF_CLK to ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
10
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 6. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to theApplication
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 6. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
11
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
The schematic of the ICS8432-51 layout example used in this
layout guideline is shown in Figure 7A. The ICS8432-51
recommended PCB board layout for this example is shown in
Figure 7B. This layout example is used as a general guideline.
The layout in the actual system will depend on the selected
component types, the density of the components, the density of
the traces, and the stack up of the P.C. board.
C1
C2
X1
U1
VCC
R7
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
M5
M6
M7
M8
N0
N1
nc
X_OUT
REF_CLK
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
10
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
C16
10u
0.01u
VEE
8432-51
VCC
VCC
R1
R3
125
125
Zo = 50 Ohm
C14
0.1u
C15
0.1u
TL1
+
-
Zo = 50 Ohm
TL2
VCC=3.3V
R2
84
R4
84
FIGURE 7A. SCHEMATIC OF RECOMMENDED LAYOUT
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example:
• The differential 50Ω output traces should have the
same length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V pin as possible.
CCA
CRYSTAL
CLOCK TRACES AND TERMINATION
The crystal X1 should be located as close as possible to the pins
24 (XTAL_OUT) and 25 (XTAL_IN). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces should
not be routed near the crystal traces.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
GND
C1
C2
VCC
X1
VIA
U1
PIN 1
C16
VCCA
C11
R7
Close to the input
pins of the
receiver
R1
R3
R2
R4
C15
TL1
C14
TL1N
TL1, TL21N are 50 Ohm
traces and equal length
FIGURE 7B. PCB BOARD LAYOUT FOR ICS8432-51
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
13
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-51.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-51 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 135mA = 467.8mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
(3.465V, with all outputs switching) = 467.8mW + 60mW = 527.8mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for devices is 125°C.
The equation for Tj is as follows: Tj = θ * Pd_total + TA
JA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.528W * 42.1°C/W = 92.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 10A. THERMAL RESISTANCE θ FOR 32-PIN LQFP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 10B. THERMAL RESISTANCE θ FOR 32-PIN VFQFN, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
14
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
V
CCO
Q1
V
OUT
R L
50
V
- 2V
CCO
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
CCO_MAX
OUT
OH_MAX
)
= 0.9V
OH_MAX
(V
– V
CCO_MAX
For logic low, V = V
= V
– 1.7V
CCO_MAX
OUT
OL_MAX
)
= 1.7V
OL_MAX
(V
– V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
/R ] * (V
– V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω) * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
/R ] * (V
– V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V – 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
15
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 11A. θ VS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 11B. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE
JA
θ by Velocity (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS8432-51 is: 3743
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
16
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 12A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0°
0.75
7°
--
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
17
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - K SUFFIX 32 LEAD VFQFN
(Ref.)
N & N
Seating Plane
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
(Ref.)
E2
2
TopView
b
e
Thermal
Base
A
(Ref.)
D2
D
N & N
Odd
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This draw-
ing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 8 below.
TABLE 12B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
Minimum
Maximum
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
8
8
5.0
D2
E
3.0
3.30
5.0
E2
L
3.0
3.30
0.50
0.30
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
18
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 13. ORDERING INFORMATION
Part/Order Number
8432CY-51LF
Marking
Package
Shipping Packaging Temperature
ICS8432CY51L
ICS8432CY51L
ICS8432C51L
ICS8432C51L
32 lead "Lead Free" LQFP
32 lead "Lead Free" LQFP
32 lead "Lead Free" VFQFN
32 lead "Lead Free" VFQFN
Tube
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8432CY-51LFT
8432CK-51LF
Tape and Reel
Tube
8432CK-51LFT
Tape and Reel
NOTE: "LF" suffix to the part number are the PB-free configuration, RoHS compliant
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
19
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Corrected labels on the Parallel & Serial Load Operations diagram.
Revised MR pin description.
Date
A
2
3
5
12/18/02
T1
T4A
Power Supply table - changed IDD to 155mA max. from 130mA max., changed IDDA to
20mA max. from 15mA max., and changed IDDO to 55mA max. from 45mA max.
B
B
2/13/03
3/12/03
9
1
Added LVDS Driver Termination Section.
General Description & Features - changed VCO min. from 200MHz to 250MHz and
replaced throughout the datasheet in: (Functional Description pg2, T3C Program.
Output Divider Func. Table pg4, and T5 Input Freq Charac. Table pg6).
- Features - changed min. Output Frequency Range from 25MHz to 31.25MHz.
T1
T2
3
3
4
5
Pin Descriptions Table - revised XTAL1, XTAL2 pin description.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Prog. VCO Freq. Func. Table - deleted 200 and 225 rows, does not apply.
C
5/9/03
T3B
T4A
Power Supply DC Characteristics Table - deleted VDDO & IDDO rows,
does not apply.
T7
6
1
AC Characteristics Table - change FOUT 25MHz min. to 31.25MHz min.
Pin Assignment - corrected XTAL pins. Pin 24 is labeled XTAL2 and pin 25 is labeled
XTAL1.
2
3
Revised Parallel & Serial Load Operations diagram.
T1
Pin Descriptions Table - corrected XTAL pins to correspond with the pin number.
Changed XTAL1 to read input and XTAL2 to read output.
C
5/28/03
10
Updated Figure 5A schematic to correspond the XTAL pins with the Pin Assignment.
11
1
16
Crystal section, corrected pin 24 to read XTAL2 and pin 25 to read XTAL1.
Features Section - added Lead-Free bullet.
Ordering Information - added Lead-Free part number.
C
D
4/8/05
T13
1
5
6
Added 32 Lead VFQFN Package for Pin Assignment.
Power Supply DC Characteristics Table - changed VCCA min. from 3.135V to VCC - 0.15V.
Crystal Characteristics Table - added Drive Level.
T4A
T6
4/13/06
9
Added LVCMOS to XTAL Interface.
10
Added Recommendations for Unused Input and Output Pins.
Added VFQFN package throughout the datasheet.
1
Changed naming convention of TEST_CLK to REF_CLK, (pin 24) XTAL2 to XTAL_OUT,
and (pin 25) XTAL1 to XTAL_IN. Changed throughout the datasheet.
T4C
T13
6
LVPECL DC Characteristics Table - corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V.
E
4/10/07
13 - 14 Power Considerations - corrected power dissipation to reflect VOH max in Table 4C.
18
Ordering Information Table - corrected ICS8432BK-51 marking to ICS8432BK51. Added
VFQFN marking.
1
Pin Assignment - corrected typo on pin 25 from XTAL_OUT to XTAL_IN.
F
F
5/13/08
11
1
18
19
Added VFQFN EPAD Thermal Release Path section.
General Description - deleted the HiperClocks logo.
VFQFN Package Dimensions - corrected D2/E2 dimensions
Ordering Information Table - per PCN# N1209-02 updated die revision ordering and
marking from "B" to "C".
T12B
T13
11/13/12
Updated footer part number from revision "B" to "C".
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
20
ICS8432CY-51 REVISION F NOVEMBER 13, 2012
ICS8432-51
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.
All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the
described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of
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