844441 [IDT]
FemtoClock SAS/ SATA Clock Generator;
| 型号： | 844441 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock SAS/ SATA Clock Generator |
| 文件： | 总15页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock® SAS/ SATA Clock Generator
844441
Datasheet
General Description
Features
The 844441 is a low jitter, high performance clock generator and a
member of the FemtoClock® family of silicon timing products. The
844441 is designed for use in applications using the SAS and SATA
interconnect. The 844441 uses an external, 25MHz, parallel
resonant crystal to generate four selectable output frequencies:
75MHz, 100MHz, 150MHz, and 300MHz. This silicon based
approach provides excellent frequency stability and reliability. The
844441 features down and center spread spectrum (SSC) clocking
techniques.
• Designed for use in SAS, SAS-2, and SATA systems
• Center (±0.17%) Spread Spectrum Clocking (SSC)
• Down (-0.23% or -0.5%) SSC
• Better frequency stability than SAW oscillators
• One differential 2.5V LVDS output
• Crystal oscillator interface designed for 25MHz
(CL = 12pF) frequency
• External fundamental crystal frequency ensures high reliability
and low aging
Applications
• SAS/SATA Host Bus Adapters
• SATA Port Multipliers
• Selectable output frequencies: 75MHz, 100MHz, 150MHz,
300MHz
• Output frequency is tunable with external capacitors
• SAS I/O Controllers
• RMS phase jitter @ 100MHz, using a 25MHz crystal
• TapeDrive and HDD Array Controllers
• SAS Edge and Fanout Expanders
• HDDs and TapeDrives
(12kHz – 20MHz): 1.1936ps (typical)
• 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• Disk Storage Enterprise
Pin Assignment
Block Diagrams
1
2
3
4
8
7
6
5
XTAL_OUT
XTAL_IN
GND
nQ
SSC_SEL0
SSC_SEL1
Q
XTAL_IN
VDD
25MHz
XTAL
00 = SSC Off
FemtoClock™
OSC
01 = 0.5% Down-spread
10 = 0.23% Down-spread
11 = 0.5% Center-spread
Q
nQ
844441
8-Lead SOIC, 3.90mm x 4.90mm Package
PLL
XTAL_OUT
SSC Output
Control Logic
Pulldown:Pulldown
SSC_SEL(1:0)
nPLL_SEL
8-Lead SOIC
Pulldown
GND
16
15
14
13
12
11
10
9
F_SEL1
GND
1
2
XTAL_IN
XTAL_OUT
XTAL_IN
FemtoClock™
PLL
25MHz
XTAL
nPLL_SEL
nQ
3
4
OSC
0
1
00 = 75MHz
01 = 100MHz
10 = 150MHz (default)
11 = 300MHz
SSC_SEL0
nc
Q
nQ
XTAL_OUT
Q
5
6
7
8
nc
nc
VDD
F_SEL0
VDD
Pullup:Pulldown
F_SEL(1:0)
SSC_SEL1
Clock Output
Control Logic
Pulldown:Pulldown
SSC_SEL(1:0)
16-Lead TSSOP
844441
16-Lead TSSOP, 4.4mm x 5.0mm Package
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Name
Type
Description
XTAL_OUT,
XTAL_IN
Input
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC_SEL0,
SSC_SEL1
Pulldown
SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
F_SEL0
F_SEL1
nPLL_SEL
Q, nQ
GND
Input
Input
Pulldown
Pullup
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
PLL Bypass pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Power supply ground.
Input
Pulldown
Output
Power
Power
Unused
VDD
Power supply pin.
nc
No connect.
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
nPLL_SEL, F_SEL[1:0], SSC_SEL[1:0]
4
pF
k
k
RPULLDOWN
RPULLUP
51
51
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Inputs
Table 3B. F_SEL[1:0] Function Table
Inputs
SSC_SEL1
SSC_SEL0
Mode
F_SEL1
F_SEL0
Output Frequency (MHz)
0 (default)
0 (default)
SSC Off
0
0
75
0
1
1
1
0
1
0.5% Down-spread
0.23% Down-spread
0.34% Center-spread
0
1 (default)
1
1
0 (default)
1
100
150
300
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Revison E, November 2, 2016
844441 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
16 Lead TSSOP
8 Lead SOIC
81.2°C/W (0 mps)
96.0°C/W (0 lfpm)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum
2.625
73
Units
V
Power Supply Voltage
Power Supply Current
2.375
2.5
IDD
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
VIH
Parameter
Test Conditions
Minimum
1.7
Typical
Maximum
Units
V
Input High Voltage
Input Low Voltage
VDD + 0.3
VIL
-0.3
0.7
5
V
F_SEL1
Input
High
Current
VDD = VIN = 2.5V
VDD = VIN = 2.5V
µA
IIH
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
150
µA
µA
µA
F_SEL1
VDD = 2.5V, VIN = 0V
VDD = 2.5V, VIN = 0V
-150
-5
Input
Low
Current
IIL
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
Table 4C. LVDS DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
VOD
VOS
50
1
1.375
50
VOS
VOS Magnitude Change
mV
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Table 4D. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Ohm
pF
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
Load Capacitance (CL)
12
pF
AC Electrical Characteristics
Table 5. AC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
F_SEL(1:0) = 00
F_SEL(1:0) = 01
F_SEL(1:0) = 10
F_SEL(1:0) = 11
Minimum
Typical
75
Maximum
Units
MHz
MHz
MHz
MHz
100
fOUT
Output Frequency
150
300
75MHz, Integration Range:
12kHz – 20MHz
1.19602
1.1936
ps
ps
ps
ps
100MHz, Integration Range:
12kHz – 20MHz
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
150MHz, Integration Range:
12kHz – 20MHz
1.22743
1.15011
300MHz, Integration Range:
12kHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
45
400
55
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using a 25MHz, 12pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plot.
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Typical Phase Noise at 100MHz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Parameter Measurement Information
V
DD
2.5V LVDS Output Load Test Circuit
RMS Phase Jitter
nQ
Q
nQ
80%
80%
VOD
20%
20%
Q
tF
tR
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Offset Voltage Setup
Differential Output Voltage Setup
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Application Information
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OU T
C2
Zo = 50 ohms
XTAL_I N
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 2A can be used
with either type of output structure. Figure 2B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
LVDS
Receiver
LVDS
Driver
ZT
Figure 2A. Standard Termination
ZT
ZO ZT
LVDS
LVDS
2
ZT
2
Receiver
Driver
C
Figure 2B. Optional Termination
LVDS Termination
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Schematic Example
Figures 3A and 3B are example 844441 application schematics for
either the 8 pin M package or the 16 pin G package. The schematic
examples focus on functional connections and are not configuration
specific. Refer to the pin description and functional tables in the
datasheet to ensure that the logic control inputs are properly set.
In order to achieve the best possible filtering, it is recommended that
the placement of the power filter components be on the device side
of the PCB as close to the power pins as possible. If space is limited,
the 0.1µF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
In this example, the device is operated at VDD = 2.5V. A 12pF parallel
resonant 25MHz crystal is used with tuning capacitors C1 = C2
=14pF, which are recommended for frequency accuracy. Depending
on the variation of the parasitic stray capacity of the printed circuit
board traces between the crystal and the Xtal_In and Xtal_Out pins,
the values of C1 and C2 might require a slight adjustment to optimize
the frequency accuracy. Crystals with other load capacitance
specifications can be used, but this will require adjusting C1 and C2.
In circuit board design, return the capacitors to ground through a
single point contact close to the package. Two examples of
terminations for LVDS receivers without built-in termination are
shown in this schematic.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
FOX 603-25-173 crystal
,'7ꢀꢁꢂꢃꢄꢅꢆꢄꢇꢈꢃꢀ&U\VWDO
R20
0
XTA L_OU T
25MHz(12pf)
X1
Zo = 50 O hm
U 1
4
2
1
8
XTA L_OU T
XTA L_IN
SS C _SE L0
SS C _SE L1
G ND
nQ
+
-
1
3
2
7
XT AL_ IN
S SC _S EL0
S SC _S EL1
nQ
Q
R1
3
6
100
Q
4
5
V DD
Zo = 50 O hm
C1
14pF
C2
14pF
C 3
0. 1uF
Place the 0.1uF bypass cap
directly adjacent to the VDD pin.
2. 5V
F B1
1
2
VD D
B LM18 BB 221S N 1
C 5
0. 1u F
C6
10uF
Z o = 50 O hm
Q
Logic Input Pin Examples
Set Logic
R3
50
Set Logic
Input to'0'
+
V DD
V DD
Input t o '1'
C 9
-
RU 1
1K
RU2
Not Install
0. 1u F
R4
50
To Logic
Input
To Logic
Z o = 50 O hm
nQ
Input
pins
pi ns
RD 1
RD2
1K
Not Install
Alternat e LVDS Termination
Figure 3A. 844441 Schematic Example
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Place one of the 0.1uF bypass caps directly adjacent to one of the VDD pins.
FB2
2.5V
2
1
VDD
BLM18BB221SN1
C13
C4
C1 1
10uF
C10
0.1uF
0.1uF
0.1uF
U7
4
8
SSC_SEL0
SSC_SEL1
SSC_SEL0
SSC_SEL1
F_SEL0
F_SEL1
10
16
F_SEL0
F_SEL1
Zo = 50 Ohm
Zo = 50 Ohm
14
nPLL_SEL
nPLL_SEL
FOX 603-25-173 crystal
12
13
Q
,'7ꢀꢁꢂꢃꢄꢅꢆꢄꢇꢈꢃꢀ&U\VWDO
Q
+
-
R2
R19
0
100
XTAL _I N
3
2
XTA L_IN
nQ
nQ
25MHz(12pf)
4
X1
XTA L_OUT
1
3
5
6
7
XT AL_ OU T
nc
nc
nc
2
C1
14pF
C2
14pF
Zo = 50 Ohm
Q
Logic Input Pin Examples
Set Logic
R5
50
Set Logic
Input to '0'
+
-
VDD
VDD
Input to '1'
C12
0.1uF
R6
50
RU3
1K
RU4
Not Install
To Logic
Inpu t
pins
To Logic
Zo = 50 Ohm
In p ut
pins
nQ
RD4
Not Install
RD3
1K
Alternate LVDS Termination
Figure 3B. 844441 Schematic Example
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 844441.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844441 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
Total Power MAX = VDD_MAX * IDD_MAX = 2.625V * 73mA = 191.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 96°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.192W * 96°C/W = 103.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (multi-layer).
Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
81.2°C/W
73.9°C/W
70.2°C/W
Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection
JA vs. Air Flow
Linear Feet per Second
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
87°C/W
82°C/W
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Reliability Information
Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
81.2°C/W
73.9°C/W
70.2°C/W
Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC
JA vs. Air Flow
Linear Feet per Second
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
87°C/W
82°C/W
Transistor Count
The transistor count for 844441 is: 3374
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Package Outline - M Suffix for 8 Lead SOIC
Table 8B. Package Dimensions for 8 Lead SOIC
All Dimensions in Millimeters
Table 8A. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
Symbol
Minimum
Maximum
N
A
A1
B
C
D
E
8
N
A
16
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
e
1.27 Basic
E
6.40 Basic
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E1
e
4.30
4.50
0.65 Basic
L
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Ordering Information
Table 9. Ordering Information
Output Frequency
(MHz)
Part/Order Number
844441DGILF
Marking
44441DIL
44441DIL
441DI75L
441DI75L
41DI100L
41DI100L
41DI150L
41DI150L
41DI300L
41DI300L
Package
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
-40C to 85C
75, 100, 150, 300
16 Lead TSSOP, Lead-Free
16 Lead TSSOP, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
8 Lead SOIC, Lead-Free
844441DGILFT
75, 100, 150, 300
Tape & Reel
Tube
844441DMI-75LF
844441DMI-75LFT
844441DMI-100LF
844441DMI-100LFT
844441DMI-150LF
844441DMI-150LFT
844441DMI-300LF
844441DMI-300LFT
75
75
Tape & Reel
Tube
100
100
150
150
300
300
Tape & Reel
Tube
Tape & Reel
Tube
Tape & Reel
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
4
Features Section, Crystal Oscillator bullet, added additional crystal recommendation.
Crystal Characteristics Table - added crystal recommendation note.
AC Characteristics Table - added additional crystal recommendation to 2nd note.
Application Schematics - in schematics, added additional crystal recommendation.
Deleted part number prefix/suffix throughout the datasheet.
T4D
T5
4
B
5/5/15
9 - 10
Updated datasheet header/footer.
C
D
9 - 10
1
Updated Application Schematics.
7/31/15
PDN #CQ-15-04 Product Discontinuance Notice –
Last Time buy Expires on August 14, 2016.
08/21/15
The 844441 datasheet is obsolete per PDN #CQ-15-04.
E
11/2/16
9 - 10
Application Schematic, IDT crystal part number was replaced by FOX part number.
©2016 Integrated Device Technology, Inc.
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Revison E, November 2, 2016
844441 Datasheet
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance spec-
ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information
contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of
IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2016 Integrated Device Technology, Inc
15
Revison E, November 2, 2016
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