853S314AFIT [IDT]
Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 MM X 7.20 MM, 1.75 M HEIGHT, MO-150, SSOP-20;
| 型号： | 853S314AFIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 MM X 7.20 MM, 1.75 M HEIGHT, MO-150, SSOP-20 光电二极管 |
| 文件： | 总16页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-4 Differential-to-2.5V,
3.3V LVPECL/ECL Fanout Buffer
ICS853S314I
Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS853S314I is a low skew 1-to-4 Differential Fanout Buffer,
designed with clock distribution in mind, accepting two clock
sources into an input MUX.The MUX is controlled by a CLK_SEL
pin. This makes the ICS853S314I very versatile, in that, it can
operate as both a differential clock buffer as well as a signal-
level translator and fanout buffer.
• Four differential ECL/LVPECL level outputs
• One differential ECL/LVPECL or single-ended input (CLKA)
One differential HSTL or single-ended input (CLKB)
• Maximum output frequency: 2.7GHz
• Additive phase jitter, RMS: 0.138ps (typical) @ 156.25MHz,
• Output skew: 50ps (maximum)
The device is designed on a SiGe process and can operate at
frequencies in excess of 2.7GHz. This ensures negligible jitter
introduction to the timing budget which makes it an ideal choice
for distributing high frequency, high precision clocks across
back planes and boards in communication systems. Internal
temperature compensation guarantees consistent performance
across various platforms.
• Part-to-part skew: 150ps (maximum)
• LVPECL and HSTL mode operating voltage supply range:
VCC = 2.5V 5ꢀ or 3.3V 5ꢀ, VEE = 0V
ECL mode operating voltage supply range:
VEE = -3.3V 5ꢀ or -2.5V 5ꢀ, VCC = 0V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Use replacement part: 8T33FS314
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC
1
2
20
19
V
CC
Q0
V
Q0
nQ0
CC
nc
CLKA
3
4
18
17
nQ0
Q1
V
CC
nCLKA
CLK_SEL
Q1
nQ1
5
6
7
16
15
14
13
12
11
nQ1
Q2
nQ2
Q3
CLKA
nCLKA
CLKB
0
VCC
VEE
Q2
nQ2
1
8
nCLKB
CLKB
9
10
nQ3
V
V
EE
nCLKB
Q3
V
CC
CC
nQ3
VEE
CLK_SEL
ICS853S314I
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm body package
F Package
VEE
Top View
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm body package
G Package
Top View
ICS853S314AFI REVISION B OCTOBER 4, 2013
1
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 3, 10
11, 20
Name
VCC
Type
Description
Power
Positive supply pins.
2
nc
Unused
Input
No connect.
Clock select input. When HIGH, selects CLKB, nCLKB inputs.
When LOW, selects CLKA, nCLKA inputs.
Default non-inverting differential clock input.
LVPECL/ECL interface levels.
4
CLK_SEL
Pulldown
Pulldown
5
CLKA
Input
Pullup/
Pulldown
6
7
8
nCLKA
CLKB
Input
Input
Input
Default inverting differential clock input. LVPECL/ECL interface levels.
Pulldown Alternative non-inverting differential clock input. HSTL interface levels.
Pullup/
nCLKB
Alternative inverting differential clock input. HSTL interface levels.
Pulldown
9
VEE
Power
Output
Output
Output
Output
Negative supply pin.
12, 13
14, 15
16, 17
18, 19
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
75
75
kΩ
kΩ
TABLE 3. GENERAL SPECIFICATIONS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VTT
Output Termination Voltage
VCC - 2
V
V
MM
HBM
CDM
LU
ESD Protection (Machine Model)
200
4000
2000
200
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-up Immunity
V
V
mA
ICS853S314AFI REVISION B OCTOBER 4, 2013
2
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
3.9V (LVPECL mode, VEE = 0V)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the de-
vice.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-3.9V (ECL mode, VCC = 0V)
-0.3V to VCC + 0.3 V
0.3V to VEE - 0.3V
Outputs, IO
Continuous Current
50mA
Package Thermal Impedance, θ
JA
20 Lead SSOP
80.8°C/W (0 lfpm)
73.2°C/W (0 lfpm)
20 Lead TSSOP
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. LVPECL/HSTL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ OR 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
Control Input CLK_SEL
VIL
VIH
IIN
Input Low Voltage
VCC -1.810
VCC -1.165
VCC -1.475
VCC -0.880
100
V
V
Input High Voltage
Input Current
VIN = VIL or VIN = VIH
µA
Clock Input Pair CLKA, nCLKA (LVPECL differential signals)
VPP
VCMR
IIN
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 2
Input Current
0.1
1.0
1.3
VCC -0.3
100
V
V
VIN = VIL or VIN = VIH
µA
Clock Input Pair CLKB, nCLKB (HSTL differential signals)
VCC = 3.3V
CC = 2.5V
0.4
0.4
0
V
V
VDIF
Differential Input Voltage; NOTE 3
V
VX
IIN
Differential Crosspoint Voltage; NOTE 4
Input Current
0.68 - 0.9
VCC -1.0
200
V
VIN = VX 0.2V
µA
LVPECL Clock Outputs (Q0:Q3, nQ0:nQ3)
VOH
Output High Voltage
VCC -1.2
VCC -1.9
VCC -1.9
VCC -1.005
VCC -1.705
VCC -1.705
VCC -0.7
VCC -1.5
VCC -1.3
V
V
V
VCC = 3.3V 5ꢀ
VOL
Output Low Voltage
V
CC = 2.5V 5ꢀ
Supply Current
Maximum Quiescent Supply Current
without Output Termination Current
NOTE 1: VPP is the minimum differential input voltage swing required to maintain device functionality.
IEE
92
mA
NOTE 2: VCMR is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within
the VCMR range and the input swing lies within the VPP specification.
NOTE 3: VDIF is the minimum differential HSTL input voltage swing required for device functionality.
NOTE 4: VX is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is
within the VX range and the input swing lies within the VPP specification.
ICS853S314AFI REVISION B OCTOBER 4, 2013
3
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4B. ECL DC CHARACTERISTICS, VCC = 0V, VEE = -2.5V 5ꢀ OR -3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
Control Input CLK_SEL
VIL
VIH
IIN
Input Low Voltage
-1.810
-1.165
-1.475
-0.880
100
V
V
Input High Voltage
Input Current
VIN = VIL or VIN = VIH
µA
Clock Input Pair CLKA,/nCLKA (ECL differential signals)
VPP
VCMR
IIN
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 2
Input Current
0.1
1.3
-0.3
100
V
V
VEE + 1.0
VIN = VIL or VIN = VIH
VEE = -3.3V 5ꢀ
µA
ECL Clock Outputs (Q0:Q3, nQ0:nQ3)
VOH
Output High Voltage
-1.2
-1.9
-1.9
-1.005
-1.705
-1.705
-0.7
-1.5
-1.3
V
V
V
VOL
Output Low Voltage
V
EE = -2.5V 5ꢀ
Supply Current
Maximum Quiescent Supply Current
without Output Termination Current
NOTE 1: VPP is the minimum differential input voltage swing required to maintain device functionality.
IEE
92
mA
NOTE 2: VCMR is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within
the VCMR range and the input swing lies within the VPP specification.
ICS853S314AFI REVISION B OCTOBER 4, 2013
4
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, (LVPECL/HSTL): VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, VEE = 0V, OR
(ECL): VEE = -3.3V 5ꢀ OR -2.5V 5ꢀ, VCC = 0V; TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VPP
VCMR
fCLK
tPD
Differential Input Voltage; NOTE 1
0.15
1.3
VCC - 0.3
2.7
V
Differential Input Crosspoint Voltage;
NOTE 2
V
EE + 1.0
V
Input Frequency; NOTE 3
GHz
ps
V
Propagation Delay, CLKA or CLKB to
Output Pair
280
0.4
650
VDIF
VX
HSTL Differential Input Voltage; NOTE 4
1.0
HSTL Input Differential Crosspoint
Voltage; NOTE 5
V
EE + 0.01
VCC - 1.0
V
fO < 300MHz
fO < 1.5GHz
0.45
0.3
0.72
0.55
0.95
0.95
50
V
V
Differential Output Voltage
(peak-to-peak)
VO(pp)
tsk(o)
Output Skew
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 6
150
156.25MHz @ 3.3V,
(1.875MHz - 20MHz)
312.5MHz @ 3.3V,
(1.875MHz - 20MHz)
0.138
0.092
ps
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
tjit
tsk(p)
tR / tF
Output Pulse Skew; NOTE 7
Output Rise/Fall Time
660MHz
75
ps
ns
20ꢀ to 80ꢀ
0.05
0.3
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
AC characteristics apply for parallel output termination of 50Ω to VTT.
NOTE 1: VPP is the minimum differential ECL/LVPECL input voltage swing required to maintain AC characteristics including
tPD and device-to-device skew.
NOTE 2: VCMR is the crosspoint of the differential ECL/LVPECL input signal. Normal AC operation is obtained when the
crosspoint is within the VCMR range and the input swing lies within the VPP specificatiion. Violation of VCMR or VPP impacts the
device propagation delay, device and part-to-part skew.
NOTE 3: The ICS853S314I is fully operational up to 2.7GHz and is characterized up to 1.5GHz.
NOTE 4:VDIF is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and
device-to-device skew.
NOTE 5: VX is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is
within the VX range and the input swing lies within the VDIF specification. Violation of VX or VDIF impacts the device
propgation delay, device and part-to-part skew.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Output pulse skew is the absolute value of the difference of the propagation delay times:⎪ tPLH - tPHL ⎪.
ICS853S314AFI REVISION B OCTOBER 4, 2013
5
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications.Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
0
-10
-20
-30
Additive Phase Jitter
3.3V @ 156.25MHz (1.875MHz to 20MHz)
= 0.138ps (typical)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
41M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
ICS853S314AFI REVISION B OCTOBER 4, 2013
6
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLKA,
nCLKB
VPP, VDIF
Cross Points
LVPECL
nQx
CLKA,
CLKB
VEE
VCMR, VX
VEE
-0.375V to -1.465V
2.5V/3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLKA,
nCLKB
nCLKA,
nCLKB
CLKA
CLKB
CLKA
CLKB
nQ0:nQ3
nQ0:nQ3
Q0:Q3
Q0:Q3
tPD
tPLH
tPHL
PROPAGATION DELAY
OUTPUT PULSE SKEW
80ꢀ
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
tF
OUTPUT RISE/FALL TIME
ICS853S314AFI REVISION B OCTOBER 4, 2013
7
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLKx/nCLKx INPUT:
LVPECL OUTPUT
For applications not requiring the use of the differential input,
both CLKx and nCLKx can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from CLKx
to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 1A and 1B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Zo = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
ICS853S314AFI REVISION B OCTOBER 4, 2013
8
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to
terminating 50Ω to V - 2V. For V = 2.5V, the V - 2V is very
close to ground level. The R3 in Figure 2B can be eliminated and
the termination is shown in Figure 2C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
R3
250
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE
ICS853S314AFI REVISION B OCTOBER 4, 2013
9
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853S314I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S314I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 92mA = 318.78mW
MAX
CC_MAX
EE_MAX
Power (outputs) = 33mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 * 33mW = 132mW
Total Power
(3.465V, with all outputs switching) = 318.78mW + 132mW = 450.78mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming a
JA
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.450W * 90.4°C/W = 125°C. This is within the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θ FOR 20-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
90.4°C/W
500
88.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
94.8°C/W
TABLE 6B. THERMAL RESISTANCE θ FOR 20-PIN SSOP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
80.8°C/W
73.2°C/W
69.2°C/W
ICS853S314AFI REVISION B OCTOBER 4, 2013
10
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 0.7V
OUT
OH_MAX
CC_MAX
)
= 0.7V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.5V
CC_MAX
OUT
OL_MAX
)
= 1.5V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.7V)/50Ω] * 0.7V = 18.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.5V)/50Ω] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 33mW
ICS853S314AFI REVISION B OCTOBER 4, 2013
11
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7A. θ VS. AIR FLOW TABLE FOR 20 LEAD SSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
80.8°C/W
73.2°C/W
69.2°C/W
TABLE 7B. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
90.4°C/W
500
88.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
94.8°C/W
TRANSISTOR COUNT
The transistor count for ICS853S314I is: 450 (approximately)
Pin compatible with CY2DP314
ICS853S314AFI REVISION B OCTOBER 4, 2013
12
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - F SUFFIX FOR 20 LEAD SSOP
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
Symbol
Minimum
Maximum
Minimum
Maximum
N
A
20
N
A
20
--
2.0
--
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
1.65
0.22
0.09
6.90
7.40
5.0
A1
A2
b
0.05
0.80
0.19
0.09
6.40
1.85
0.38
0.25
7.50
8.20
5.60
c
c
D
D
E
6.40 BASIC
0.65 BASIC
E
E1
e
4.30
4.50
E1
e
0.65 BASIC
L
0.45
0°
0.75
8°
L
0.55
0°
0.95
8°
α
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-150
Reference Document: JEDEC Publication 95, MO-153
ICS853S314AFI REVISION B OCTOBER 4, 2013
13
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
853S314AFI
853S314AFIT
853S314AFILF
853S314AFILFT
853S314AGI
ICS853S314AI
ICS853S314AI
ICS53S314AIL
ICS53S314AIL
ICS53S14AGI
ICS53S14AGI
ICS3S314AGIL
ICS3S314AGIL
20 lead SSOP
20 lead SSOP
2500 tape & reel
tube
20 lead "Lead-Free" SSOP
20 lead "Lead-Free" SSOP
20 lead TSSOP
2500 tape & reel
tube
853S314AGIT
853S314AGILF
853S314AGILFT
20 lead TSSOP
2500 tape & reel
tube
20 lead "Lead-Free" TSSOP
20 lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS853S314AFI REVISION B OCTOBER 4, 2013
14
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
Page
14
1
Date
T9
Ordering Information Table - Added "Lead-Free" Marking.
1/24/09
2/6/13
10/4/13
A
Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)
PDN# N-13-03R1 - Added Use replacement part: 8T33FS314
B
1
ICS853S314AFI REVISION B OCTOBER 4, 2013
15
©2013 Integrated Device Technology, Inc.
ICS853S314I Data Sheet
LOW SKEW, 1-TO4 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Techical Support
netcom@idt.com
+480-763-2056
800-345-7015 (inside USA)
+408-284-8200 (outside
USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All
information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described
products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation
or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of
the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property
of IDT or their respective third party owners.
Copyright 2013. All rights reserved.
相关型号：
853S314AGI
Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 MM X 6.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
IDT
853S314AGILFT
Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 MM X 6.50 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20
IDT
853S314AGIT
Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 4.40 MM X 6.50 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明