853S54AKILF [IDT]
Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer;
| 型号： | 853S54AKILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer 逻辑集成电路 |
| 文件： | 总21页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 2:1, 1:2 Differential-to-LVPECL/ECL
Multiplexer
ICS853S54I
DATA SHEET
General Description
Features
The ICS853S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplex-
er allows one of 2 inputs to be selected onto one output pin and the
1:2 MUX switches one input to one of two outputs. This device is
useful for multiplexing multi-rate Ethernet PHYs which have 100 M
bit and 1000 bit transmit/receive pairs onto an optical SFP module
which has a single transmit/receive pair. See Application Section for
further information.
• Three differential LVPECL output pairs
• Three differential LVPECL clock inputs
• PCLKx/nPCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML
• Maximum output frequency: 2.5GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: QA, nQA: 450ps (maximum)
The ICS853S54I is optimized for applications requiring very high
performance and has a maximum operating frequency of 2.5GHz.
The device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
QBx, nQBx: 420ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packaging
Pin Assignment
Block Diagram
CLK_SELA
Pulldown
Pulldown
PCLKA0
nPCLKA0
16 15 14 13
0
Pullup/Pulldown
1
2
3
QB0
nQB0
QB1
12
11
10
PCLKA0
nPCLKA0
PCLKA1
nPCLKA1
QA
nQA
Pulldown
PCLKA1
nPCLKA1
Pullup/Pulldown
1
nQB1
4
9
5
6
7
8
Pulldown
PCLKB
nPCLKB
QB0
Pullup/Pulldown
nQB0
ICS853S54I
QB1
nQB1
16-Lead VFQFN
Top View
Pulldown
CLK_SELB
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
Name
Type
Description
QB0, nQB0
QB1, nQB1
PCLKB
Output
Output
Input
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Non-inverting LVPECL/ECL differential clock input.
3, 4
5
Pulldown
Pullup/
Pulldown
6
nPCLKB
Input
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Clock select pin for QBx outputs. When HIGH, selects QB1/nQB1 outputs.
When LOW, selects QB0/nQB0 outputs. LVCMOS/LVTTL interface levels.
7
8
CLK_SELB
VEE
Input
Power
Input
Input
Input
Pulldown
Negative supply pin.
Pullup/
Pulldown
9
nPCLKA1
PCLKA1
nPCLKA0
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Non-inverting LVPECL/ECL differential clock input.
Inverting differential LVPECL clock input. VCC/2 default when left floating.
10
11
Pulldown
Pullup/
Pulldown
12
13
PCLKA0
VCC
Input
Pulldown
Non-inverting LVPECL/ECL differential clock input.
Positive supply pin.
Power
Clock select pin for QA output. When HIGH, selects QA output. When LOW,
selects nQA output. LVCMOS/LVTTL interface levels.
14
CLK_SELA
nQA, QA
Input
Pulldown
15, 16
Output
Differential output pair. LVPECL/ECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
2
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
RPullup/Pulldown Resistor
RPULLDOWN
RVCC/2
37.5
37.5
k
k
Function Tables
Table 3A. Control Input Function Table, (Bank A)
Table 3B. Control Input Function Table, (Bank B)
Bank A
Bank B
Control Input
CLK_SELA
0 (default)
1
Outputs
Control Input Outputs
QA, nQA
CLK_SELB
0 (default)
1
QB0, nQB0
QB1, nQB1
Selects PCLKA0, nPCLKA0
Selects PCLKA1, nPCLKA1
Follows PCLKB input
Logic Low
Logic Low
Follows PCLKB input
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
4.6V (LVPECL mode, VEE = 0V)
-4.6V (ECL mode, VCC = 0V)
-0.5V to VCC + 0.5V
0.5V to VEE – 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Operating Termperature Range, TA
Storage Temperature, TSTG
-40C to 85C
-65C to 150C
74.7C/W (0 mps)
Package Thermal Impedance, JA
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.465V, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Positive Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.625
45
Units
V
2.375
2.5
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 2.375V to 3.465V, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
0.7VCC
-0.3
Typical
Maximum
VCC + 0.3
0.3VCC
Units
VIH
VIL
Input High Voltage
V
V
Input Low Voltage
Input High Current
CLK_SELA,
CLK_SELB
IIH
IIL
VCC = VIN
VCC = VIN
150
μA
μA
CLK_SELA,
CLK_SELB
Input Low Current
-150
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 0V, VEE = -3.465V to -2.375V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
0.3VEE
Typical
Maximum
0.3
Units
VIH
VIL
Input High Voltage
V
V
Input Low Voltage
Input High Current
VEE – 0.3
0.7VEE
CLK_SELA,
CLK_SELB
IIH
IIL
VCC = VIN
VCC = VIN
150
μA
μA
CLK_SELA,
CLK_SELB
Input Low Current
-150
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Table 4D. LVPECL DC Characteristics, VCC = 2.375V to 3.465V, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VCC = VIN
Minimum
Typical
Maximum
200
Units
μA
μA
μA
μA
V
PCLKA[0:1], PCLKB
nPCLKA[0:1], nPCLKB
PCLKA[0:1], PCLKB
nPCLKA[0:1], nPCLKB
Input
IIH
High Current
VCC = VIN
200
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-200
-200
0.15
Input
IIL
Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
1.2
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.2
VCC
V
VOH
Output High Current; NOTE 3
Output Low Current; NOTE 3
Peak-to-Peak Output Voltage Swing
VCC – 1.125
VCC – 1.895
0.6
VCC – 1.005
VCC – 1.78
VCC – 0.875
VCC – 1.62
1.0
V
V
V
VOL
VSWING
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
NOTE 3: Outputs terminated with 50 to VCC – 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 2.375V to 3.465V, VEE = 0V or VCC = 0V, VEE = -3.465V to -2.375V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
2.5
Units
GHz
ps
fOUT
Output Frequency
QA, nQA
225
195
335
305
445
Propagation Delay;
NOTE 1
tPD
QBx, nQBx
420
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
200
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section; NOTE 4
622.08MHz Integration
Range: 12kHz - 20MHz
tjit
0.035
ps
ƒOUT = 622.08MHz,
MUX_ISOLATION MUX Isolation; NOTE 5
tR / tF Output Rise/Fall Time
65
dB
ps
VPP = 800mV
20% to 80%
75
155
250
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters are measured 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Measured using clock input at 622.08MHz.
NOTE 5: Q/nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram.
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz band
at a specified offset from the fundamental frequency to the power
value of the fundamental. This ratio is expressed in decibels (dBm)
or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.035ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator”.
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Parameter Measurement Information
2V
V
CC
SCOPE
VCC
Qx
nPCLKA[0:1},
nPCLKB
VPP
VCMR
Cross Points
PCLKA[0:1},
PCLKB
nQx
VEE
V
EE
-0.375V to -1.465V
LVPECL Output Load AC Test Circuit
Differential Input Level
nPCLKA[0:1},
nPCLKB
Part 1
nQx
PCLKA[0:1},
PCLKB
Qx
nQA,
nQB[0:1]
Part 2
nQy
Qy
QA,
QB[0:1]
tPD
tsk(pp)
Part-to-Part Skew
Propagation Delay
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
nQA,
nQB[0:1]
MUX_ISOL = A0 – A1
QA,
QB[0:1]
MUX selects static input
A1
ƒ
Frequency
(fundamental)
Output Rise/Fall Time
MUX Isolation
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and
VCC
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from PCLK to
ground.
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
LVPECL Differential Clock Input Interface (3.3V)
The PCLK /nPCLK accepts LVDS, LVPECL, and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
C1
PCLK
Zo = 50Ω
Zo = 50Ω
R5
100Ω
VBB
PCLK
C2
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
nPCLK
R1
1k
R2
1k
LVPECL
Input
LVPECL
R1
R2
84Ω
84Ω
C3
0.1µF
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
3.3V
2.5V
R3
R4
120
120
Zo = 60Ω
Zo = 60Ω
PCLK
nPCLK
LVPECL
Input
SSTL
R1
120
R2
120
Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVPECL
Driver with AC Couple
Figure 2D. PCLK/nPCLK Input Driven by an SSTL Driver
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
PCLK
R1
100Ω
nPCLK
Zo = 50Ω
nPCLK
LVPECL
LVPECL
Input
CML
CML Built-In Pullup
Input
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
Figure 2F. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
LVPECL Clock Input Interface (2.5V)
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. The differential signal must meet the VPP and VCMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
PCLK
nPCLK
Figure 2A. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
LVPECL
Figure 2C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
3.3V
R3
R4
125
125
3.3V
3.3V
Zo = 50
+
_
Input
Z
o = 50
R1
84
R2
84
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECLdriver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 6B can be eliminated and the termination is
shown in Figure 6C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
R3
250Ω
250Ω
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
2.5V LVPECL Driver
R2
R4
62.5Ω
62.5Ω
R3
18Ω
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
Figure 6C. 2.5V LVPECL Driver Termination Example
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
A Typical Application for the ICS853S54I
Used to connect a multi-rate PHY with the Tx/Rx pins of an SFP
Module.
Problem Addressed: How to map the 2 Tx/Rx pairs of the multi-rate
PHY to the single Tx/Rx pair on the SFP Module.
MULTI-RATE PHY
SFP MODULE
Tx
100BaseFX
Rx
Rx
?
Tx
Tx
1000BaseX
Rx
Mode 1, 100BaseX Connected to SFP
All lines are differential pairs, but drawn as single-ended to simplify
the drawing.
Bold red lines
signal path.
are active connections highlighting the
CLK_SELA = 0
MULTI-RATE PHY
CLKA0
SFP MODULE
Tx
0
QA
Rx
CLKA1
QB0
1
100BaseFX
CLKB
Tx
Rx
QB1
CLK_SELB = 0
Tx
Rx
ICS85354
1000BaseX
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Mode 2, 100BaseX Connected to SFP
All lines are differential pairs, but drawn as single-ended to simplify
the drawing.
Bold red lines
signal path.
are active connections highlighting the
CLK_SELA = 1
MULTI-RATE PHY
CLKA0
SFP MODULE
Tx
0
QA
Rx
Tx
CLKA1
1
100BaseFX
CLKB
QB0
QB1
Rx
CLK_SELB = 1
Tx
Rx
ICS853S54I
1000BaseX
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S54I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S54I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 45mA = 155.925mW
Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 3 * 32mW = 96mW
Total Power_MAX (3.3V, with all outputs switching) = 155.925mW + 96mW = 251.925mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.252W * 74.7°C/W = 103.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection
JA by Velocity
0
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
The LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.875V
(VCC_MAX – VOH_MAX) = 0.875V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.62V
(VCC_MAX – VOL_MAX) = 1.62V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.875V)/50] * 0.875V = 19.69mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.62V)/50] * 1.62V = 12.31mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
JA by Velocity
0
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
Transistor Count
The transistor count for ICS853S54I is: 296
This is a suggested replacement for ICS85354
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Package Outline Drawings (Sheet 1)
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Package Outline Drawings (Sheet 2)
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Ordering Information
Table 9. Ordering Information
Part/Order Number
853S54AKILF
853S54AKILFT
Marking
S54A
S54A
Package
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
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ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
8
Deleted HiperClockS Logo. Added CML to 3rd bullet.
Added figures 2D, 2E and 2F.
A
T9
-
10/30/2012
5/27/2017
19
Deleted quantity from tape and reel.
B
18
Updated the package outline drawings.
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