87001BG-01T [IDT]
Clock Driver, 87001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-16;
| 型号： | 87001BG-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, 87001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LVCMOS/LVTTL CLOCK DIVIDER
ICS87001-01
General Description
Features
The ICS87001-01 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5,
• One LVCMOS / LVTTL output, 15Ω output impedance
• Selectable LVCMOS / LVTTL clock inputs
• Maximum output frequency: 250MHz
• Part-to-part skew: TBD
S
IC
÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/Divider
and a member of theHiPerClockS™ family of High
Performance Clock Solutions from IDT. The
ICS87001-01 has selectable clock inputs that
HiPerClockS™
accept single ended input levels. Output enable pin controls
whether the output is in the active or high impedance state.
• Power supply modes:
Core/Output
3.3V/3.3V
The ICS87001-01 is characterized at 3.3V, 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed part-to-part skew characteristics make the
ICS87001-01 ideal for those applications demanding well defined
performance and repeatability.
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Pulldown
CLK_SEL
OE
VDD
1
2
16
15
VDDO
nc
N Output Divider
N2:N0
14
13
CLK0
CLK_SEL
CLK1
N2
Q
nc
3
4
0 0 0 ÷1 (default)
Pulldown
CLK0
0
0 0 1 ÷2
12
11
10
9
GND
nc
nc
5
6
7
8
0 1 0 ÷3
Q
0 1 1 ÷4
Pulldown
CLK1
1
N1
N0
1 0 0 ÷5
GND
1 0 1 ÷6
1 1 0 ÷8
1 1 1 ÷16
ICS87001-01
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm
package body
3
Pulldown
N2:N0
G Package
Top View
Pullup
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 1. Pin Descriptions
Number
Name
Type
Pullup
Description
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
1
OE
Input
2
VDD
Power
Input
Power supply pin.
3, 5
CLK0, CLK1
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input.
Pulldown
4
CLK_SEL
Input
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
6, 7, 8
9, 12
N2, N1, N0
GND
Input
Power
Unused
Pulldown N divider pins. LVCMOS/LVTTL interface levels. See Table 3.
Power supply ground.
No connect.
10, 11, 13, 15
nc
Single-ended clock output. 15Ω output impedance.
LVCMOS/LVTTL interface levels.
14
16
Q
Output
Power
VDDO
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
10
15
kΩ
kΩ
pF
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
Output Impedance
ROUT
Ω
Function Tables
Table 3. Programmable Output Divider Function Table
Inputs
N2
0
N1
0
N0
0
N Divider Value
Output Frequency (MHz)
÷1 (default)
250
125
0
0
1
÷2
÷3
0
1
0
83.333
62.5
0
1
1
÷4
1
0
0
÷5
50
1
0
1
÷6
41.667
31.25
15.625
1
1
0
÷8
1
1
1
÷16
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO+ 0.5V
100.3°C/W (0 mps)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%,TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
VDDO
IDD
3.135
3.3
3.465
V
40
mA
mA
IDDO
1
Table 4B. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO =2.5V 5%, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
VDDO
IDD
2.375
2.5
2.625
V
40
mA
mA
IDDO
1
Table 4C. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO =1.8V 0.15V, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
VDDO
IDD
1.65
1.8
1.95
V
40
mA
mA
IDDO
1
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
3
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 4D. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
2.625
2.625
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
39
mA
mA
IDDO
1
Table 4E. Power Supply DC Characteristics, VDD = 2.5V 5%, VDDO =1.8V 0.15V, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
Units
V
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
VDDO
IDD
1.65
1.8
1.95
V
39
mA
mA
IDDO
1
Table 4F. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
VDD = 3.465V
VDD = 2.625V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
DD = 3.465V
DD = 2.625V
Input Low Voltage
V
0.7
CLK0, CLK1,
N[2:0], CLK_SEL
V
DD = VIN = 3.465V or 2.625V
150
5
µA
µA
µA
Input
High Current
IIH
OE
VDD = VIN = 3.465V or 2.625V
DD = 3.465V or 2.625V, VIN = 0V
CLK0, CLK1,
N[2:0], CLK_SEL
V
-5
Input
Low Current
IIL
OE
VDD = 3.465V or 2.625V, VIN = 0V
DDO = 3.3V 5%
VDDO = 2.5V 5%
DDO = 1.8V 0.15V
DDO = 3.3V 5%
VDDO = 2.5V 5%
DDO = 1.8V 0.15V
-150
2.6
µA
V
V
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.8
V
V
1.5
V
V
0.5
0.5
0.4
V
VOL
V
V
V
IOZL
IOZH
Output Hi-Z Current Low
Output Hi-Z Current High
-5
µA
µA
5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
4
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
Propagation Delay,
Low to High; NOTE 1
tPD
4.3
ns
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
ps
ps
%
t
R / tF
20% to 80%
700
50
odc
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
5
5
ns
ns
tDIS
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
Table 5B. AC Characteristics, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
Propagation Delay,
Low to High; NOTE 1
tPD
4.6
ns
tsk(pp)
tR / tF
odc
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
ps
ps
%
20% to 80%
800
50
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
5
5
ns
ns
tDIS
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
5
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 5C. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.15V, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
Propagation Delay,
Low to High; NOTE 1
tPD
5
ns
tsk(pp)
tR / tF
odc
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
ps
ns
%
20% to 80%
1
50
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
5
5
ns
ns
tDIS
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production..
Table 5D. AC Characteristics, VDD = VDDO = 2.5V 5%, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
Propagation Delay,
Low to High; NOTE 1
tPD
4.7
ns
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
ps
ps
%
t
R / tF
20% to 80%
900
50
odc
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
5
5
ns
ns
tDIS
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
6
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Table 5E. AC Characteristics, VDD = 2.5V 5%, VDDO = 1.8V 0.15V, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
Propagation Delay,
Low to High; NOTE 1
tPD
5
ns
tsk(pp)
tR / tF
odc
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time; NOTE 4
Output Duty Cycle
ps
ns
%
20% to 80%
1.1
50
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
5
5
ns
ns
tDIS
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
7
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Parameter Measurement Information
2.05V 5%
1.25V 5%
1.65V 5%
SCOPE
V
DD,
SCOPE
V
V
DD
DDO
Qx
V
DDO
LVCMOS
Qx
GND
LVCMOS
GND
-1.65V 5%
-1.25V 5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
2.4V 5%
1.25V 5%
0.9V 0.075V
SCOPE
SCOPE
V
V
DD
DD,
V
DDO
V
DDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V 5%
-0.9V 0.075V
3.3V Core/1.8V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
1.6V 5%
0.9V 0.075V
Part 1
VDDO
2
SCOPE
V
DD
Qx
V
DDO
Qx
Part 2
VDDO
2
GND
LVCMOS
Qy
tsk(pp)
-0.9V 0.075V
2.5V Core/1.8V LVCMOS Output Load AC Test Circuit
Part-to-Part Skew
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
8
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Parameter Measurement Information, continued
VDD
80%
tF
80%
tR
2
CLK0, CLK1
20%
20%
Q
VDDO
2
Q
t
PD
Output Rise/Fall Time
Propagation Delay
VDDO
2
Q
tPW
tPERIOD
tPW
x 100%
odc =
tPERIOD
Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input Pins
CLK Inputs
Inputs:
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
9
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Reliability Information
Table 6. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
96.0°C/W
93.9°C/W
Transistor Count
The transistor count for ICS87001-01: 2781
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
10
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Ordering Information
Table 8. Ordering Information
Part/Order Number
87001BG-01
87001BG-01T
87001BG-01LF
87001BG-01LFT
Marking
Package
16 Lead TSSOP
16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
87001B01
87001B01
7001B01L
7001B01L
“Lead-Free” 16 Lead TSSOP
“Lead-Free” 16 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
11
ICS87001BG-01 REV. A MAY 1, 2009
ICS87001-01
LVCMOS/LVTTL CLOCK DIVIDER
PRELIMINARY
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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