8725AM-21T [IDT]
PLL Based Clock Driver, 8725 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20;
| 型号： | 8725AM-21T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8725 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总18页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DIFFERENTIAL-TO-HSTL ZERO DELAY
CLOCK GENERATOR
ICS8725-21
Not Recommend for New Designs - 10/23/2013
For replacement device use ICS8725BY-01LF
General Description
NRND
Features
The ICS8725-21 is a highly versatile 1:1 Differential- to-HSTL
Clock Generator and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT. The CLK, nCLK pair
can accept most standard differential input levels. The
ICS8725-21 has a fully integrated PLL and can be configured as
zero delay buffer, multiplier or divider, and has an output frequency
range of 31.25MHz to 630MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios: 8:1, 4:1,
2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to
achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output
dividers.
• One differential HSTL output pair
One differential feedback output pair
• Differential CLK/nCLK input pair
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
• Output frequency range: 31.25MHz to 630MHz
• Input frequency range: 31.25MHz to 630MHz
• VCO range: 250MHz to630MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 35ps (maximum)
• Output skew: 50ps (maximum)
• Static phase offset: 30ps 125ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Industrial temperature information available upon request
Pin Assignment
Block Diagram
Pullup
PLL_SEL
CLK
nCLK
MR
1
2
20 nc
Q
nQ
19
SEL1
÷1, ÷2, ÷4, ÷8,
0
3
4
18 SEL0
÷16, ÷32,÷64
VDD
17
VDD
Pulldown
Pullup
CLK
nCLK
nFB_IN
FB_IN
SEL2
5
6
7
16 PLL_SEL
QFB
nQFB
1
15
14
13
12
11
VDDA
SEL3
GND
nQFB
QFB
8
VDDO
PLL
9
10
Q
nQ
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Pulldown
Pullup
FB_IN
nFB_IN
ICS8725-21
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Top View
SEL0
SEL1
SEL2
SEL3
MR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
CLK
Type
Description
1
2
Input
Input
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
3
MR
Input
Pulldown
4, 17
5
VDD
Power
Input
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 9.
nFB_IN
Pullup
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 10.
6
FB_IN
Input
Input
Pulldown
7, 14,
18, 19
SEL2, SEL3,
SEL0 SEL1
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
8
9, 10
11, 12
13
GND
nQFB, QFB
nQ/Q
Power
Output
Output
Power
Power
Power supply ground.
Differential feedback output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Output supply pin.
VDDO
15
VDDA
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
16
20
PLL_SEL
Input
Pullup
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
nc
Unused
No connect.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
k
RPULLDOWN Input Pulldown Resistor
k
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Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)*
250 - 630
Q/nQ
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
125 - 315
62.5 - 157.5
31.25 - 78.75
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
125 - 315
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
62.5 - 157.5
31.25 - 78.75
31.25 - 78.75
x2
x2
x4
x4
x8
*NOTE: VCO frequency range for all configurations above is 250MHz to 630MHz.
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Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q/nQ, QFB/nQFB
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
46.2C/W (0 lfpm)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
Maximum
3.465
3.465
2.0
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.3
V
1.8
V
137
mA
mA
mA
IDDA
IDDO
17
0
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
2
VDD + 0.3
Input Low Voltage
-0.3
0.8
150
5
V
SEL[0:3], MR
PLL_SEL
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
µA
µA
µA
µA
IIH
Input High Current
SEL[0:3], MR
PLL_SEL
V
V
-5
IIL
Input Low Current
-150
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Table 4C. Differential DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
CLK, FB_IN
VDD = VIN = 3.465V
150
5
IIH
Input High Current
nCLK, nFB_IN
VDD = VIN = 3.465V
µA
VDD = 3.465V,
VIN = 0V
CLK, FB_IN
-5
µA
µA
IIL
Input Low Current
VDD = 3.465V,
nCLK, nFB_IN
-150
VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD – 0.85
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. HSTL DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.4
0.4
60
V
V
VOL
Output Low Voltage; NOTE 1
VOX
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
0.6
%
V
VSWING
1.1
NOTE 1: Outputs termination with 50 to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 5. Input Frequency Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
Typical
Maximum
630
Units
MHz
MHz
31.25
FIN
Input Frequency
CLK, nCLK
630
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AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Parameter Symbol
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ns
630
4.5
155
50
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
PLL_SEL = 0V, f 700MHz
PLL_SEL = 3.3V
3.2
-95
tsk(Ø)
tsk(o)
tjit(cc)
tjit()
tL
30
ps
PLL_SEL = 0V
ps
35
ps
50
ps
1
ms
ps
tR / tF
tPW
Output Rise/Fall Time
20% to 80%
300
700
Output Pulse Width
tPERIOD/2 - 85 tPERIOD/2 tPERIOD/2 + 85
ps
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked
and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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Parameter Measurement Information
3.3V 5%
1.8V 0.2V
V
DD
SCOPE
Qx
V
DD,
V
nCLK
CLK
DDA
V
DDO
VPP
VCMR
Cross Points
HSTL
nQx
GND
GND
0V
GND = 0V
3.3V Core/1.8V Output Load AC Test Circuit
Differential Input Level
nCLK
CLK
VOH
VOL
nQx
Qx
nQ, nQFB
VOH
VOL
Q, QFB
nQy
Qy
➤
t(Ø)
➤
tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges)
Phase Jitter and Static Phase Offset
Output Skew
nQ, nQFB
VDDO
nQ, nQFB
Q, QFB
VDDO
2
VDDO
2
2
Q, QFB
Pulse Width
tcycle n
tcycle n+1
tPERIOD
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
Cycle-to-Cycle Jitter
Output Pulse Width
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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Parameter Measurement Information, continued
nCLK
80%
tF
80%
tR
CLK
VSWING
20%
nQ, nQFB
Q, QFB
Clock
Outputs
20%
tPD
Propagation Delay
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
To achieve optimum jitter performance, power supply isolation is
required. The ICS8725-21 provides separate power supplies to
isolate any high switching noise from the outputs to the internal
PLL. VDD, VDDA and VDDO should be individually connected to the
power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic
VDD pin and also shows that VDDA requires that an additional 10
resistor along with a 10F bypass capacitor be connected to the
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
VDDA pin. The 10 resistor can also be replaced by a ferrite bead.
Figure 1. Power Supply Filtering
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
-
V_REF
C1
0.1uF
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50Ω
R2
50Ω
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
*R3
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
Differential
Input
Differential
Input
*R4
SSTL
HCSL
R1
R2
120Ω
120Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
IDT™ / ICS™ HSTL ZERO DELAY CLOCK GENERATOR
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DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR
Schematic Example
Figure 4 shows a schematic example of the ICS8725-21. In this
example, the input is driven by an HCSL driver. The zero delay
buffer is configured to operate at 155.52MHz input and 77.75MHz
output. The logic control pins are configured as follows:
SEL[3:0] = 0101
For ICS8725-21, the decoupling capacitors should be physically
located near the power pin.
PLL_SEL = 1
R7
VDD
3.3V
VDDA
(155.5 MHz)
U1
Zo = 50 Ohm
10
1
20
19
18
17
16
15
14
13
12
11
C11
0.01u
CLK
2
nc
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
Q
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
C16
10u
nCLK
3
4
5
6
7
8
9
10
MR
VDD
VDD
Zo = 50 Ohm
nFB_IN
FB_IN
SEL2
GND
nQFB
QFB
SEL2
HCSL
VDD
VDDO
Zo = 50 Ohm
R8
50
R9
50
+
nQ
R1
50
R2 ICS8725-21
50
C3
0.1uF
Zo = 50 Ohm
-
LVHSTL_input
(77.75 MHz)
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
R4
50
R5
50
PLL_SEL
SEL0
SEL1
SEL2
SEL3
VDD=3.3V
Bypass capacitors located
near the power pins
VDDO=1.8V
(U1-4) VDD
(U1-17)
SEL[3:0] = 0101,
Divide by 2
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
C1
0.1uF
C2
0.1uF
SP = Space (i.e. not intstalled)
Figure 4. ICS8725-21 HSTL Buffer Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8725-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8725-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (137mA + 17mA) = 533.6mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 533.6mW + 32.8mW = 566.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.566W * 39.7°C/W = 111°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 7. Thermal Resistance JA for 20 Lead SOIC, Forced Convection
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDD
Q1
VOUT
RL
50Ω
Figure 5. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX
)
Pd_L = (VOL_MAX/RL) * (VDDO_MAX- VOL_MAX
)
Pd_H = (1.0V/50) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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Reliability Information
Table 8. JA vs. Air Flow Table for a 20 Lead TSSOP
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS8725-21 is: 2969
Package Outline and Package Dimensions
Package Outline - M Suffix for 20 Lead SOIC
Table 9. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
A1
A2
B
C
D
E
20
2.65
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
e
1.27 Basic
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
Reference Document: JEDEC Publication 95, MS-013, MS-119
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Ordering Information
Table 10. Ordering Information
Part/Order Number
ICS8725AM-21
ICS8725AM-21T
ICS8725AM-21LF
ICS8725AM-21LFT
Marking
Package
20 Lead SOIC
20 Lead SOIC
Shipping Packaging
Tube
1000 Tape & Reel
Tube
Temperature
0C to 70C
0C to 70C
0C to 70C
0C to 70C
ICS8725AM-21
ICS8725AM-21
ICS8725AM-21LF
ICS8725AM-21LF
“Lead-Free” 20 Lead SOIC
“Lead-Free” 20 Lead SOIC
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
T10
14
Ordering Information Table - added Lead-Free marking and note.
6/9/05
2
8
Pin Descriptions Table - corrected MR description.
Added Recommendations for Unused Input and Output Pins.
A
T1
5/22/06
11
12
Updated Differential Clock Input Interface section.
Updated Schematic Example section.
A
B
2/27/08
1
Added - NRND - Not Recommended for New Designs
10/23/13
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We’ve Got Your Timing Solution
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www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2013. All rights reserved.
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