8SLVD1212NLGI/W [IDT]
1:12, LVDS Output Fanout Buffer;
| 型号： | 8SLVD1212NLGI/W |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 1:12, LVDS Output Fanout Buffer |
| 文件： | 总21页 (文件大小：555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1:12, LVDS Output Fanout Buffer
8SLVD1212
Datasheet
General Description
Features
The 8SLVD1212 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1212 is
characterized to operate from a 2.5V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1212 ideal for those clock distribution applications demanding
well-defined performance and repeatability. Two selectable
differential inputs and twelve low skew outputs are available. The
integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
• Twelve low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL, CML
• Maximum input clock frequency: 2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pins
• Output skew: 45ps (max)
• Propagation delay: 310ps (typical)
• Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz - 20MHz: 77fs (typical)
• Maximum device current consumption (IDD): 213mA
• 2.5V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Pin Assignment
38 37 36 35 34 33 32 31
39
40
1
2
SEL
30
29
28
27
26
25
24
23
22
21
GND
nQ7
PCLK1
nPCLK1
VREF1
VDD
3
Q7
nQ6
Q6
4
5
8SLVD1212
VDD
nQ5
Q5
6
VREF0
nPCLK0
7
nQ4
Q4
8
PCLK0
nc
9
GND
10
11 12
13 14
16 17 18 19 20
15
40-Lead VFQFN
6.0mm x 6.0mm x 0.9mm package body
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8SLVD1212 Datasheet
Block Diagram
Q0
nQ0
Voltage
Reference
VREF0
Q1
nQ1
VDD
Q2
nQ2
PLCK0
Q3
nPLCK0
nQ3
Q4
nQ4
fREF
GND
VDD
Q5
nQ5
Q6
PLCK1
nQ6
nPLCK1
VDD
Q7
nQ7
GND
SEL
Q8
nQ8
Q9
GND
nQ9
Q10
nQ10
Voltage
Reference
VREF1
Q11
nQ11
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8SLVD1212 Datasheet
Pin Descriptions and Characteristics
1
Table 1. Pin Descriptions
Number
Name
SEL
Type
Description
Pullup/
Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
1
2
3
Input
Input
Input
PCLK1
nPCLK1
Pulldown
Non-inverting differential clock/data input.
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
4
5
6
7
VREF1
VDD
Output
Power
Power
Output
Bias voltage reference for the PCLK1, nPCLK1 inputs.
Power supply pins.
VDD
Power supply pins.
VREF0
Bias voltage reference for the PCLK0, nPCLK0 inputs.
Pullup/
Pulldown
8
nPCLK0
Input
Inverting differential clock/data input. VDD/2 default when left floating.
9
PCLK0
nc
Input
Unused
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Output
Output
Pulldown
Non-inverting differential clock/data input.
Do not connect.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
Q0
Power supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VDD
GND
Q4
Power supply pins.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
GND
VDD
Q8
Power supply ground.
Power supply pins.
Differential output pair. LVDS interface levels.
nQ8
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8SLVD1212 Datasheet
1
Table 1. Pin Descriptions
Number
34
Name
Q9
Type
Description
Output
Output
Output
Output
Output
Output
Power
Power
Differential output pair. LVDS interface levels.
35
nQ9
36
Q10
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
37
nQ10
Q11
38,
39
nQ11
VDD
40
Power supply pins.
GND_EP
Exposed pad of package. Connect to GND.
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
2
RPULLDOWN
RPULLUP
50
50
k
k
Function Table
Table 3. SEL Input Function Table
SEL
1
Operation
0
1
PCLK0, nPCLK0 is the selected differential clock input.
PCLK1, nPCLK1 is the selected differential clock input.
Input buffers are disabled and outputs are static.
Open
NOTE 1: SEL is an asynchronous control.
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8SLVD1212 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Input Sink/Source, IREF
±2mA
Maximum Junction Temperature, TJ,MAX
125°C
Storage Temperature, TSTG
-65°C to 150°C
2000V
ESD - Human Body Model1
ESD - Charged Device Mode1
500V
NOTE 1: According to JEDEC/JS-001-2012/ 22-C101E.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Power Supply Voltage
2.375
2.5V
2.625
V
Q0 to Q11 terminated 100
IDD
Power Supply Current
184
213
mA
between nQx, Qx
Table 4B. LVCMOS/LVTTL DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
VMID
VIH
Parameter
Test Conditions
Floating
Minimum
Typical
Maximum
Units
V
Input voltage
VDD / 2
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
0.7 * VDD
-0.3
VDD + 0.3
0.2 * VDD
150
V
VIL
V
IIH
SEL
SEL
VDD = VIN = 2.625V
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
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Table 4C. Differential Inputs Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
PCLK0,
nPCLK0
PCLK1,
nPCLK1
Input
High Current
IIH
VIN = VDD = 2.625V
150
µA
PCLK0,
PCLK1
V
IN = 0V, VDD = 2.625V
IN = 0V, VDD = 2.625V
-10
-150
µA
µA
V
Input
Low Current
IIL
nPCLK0,
nPCLK1
V
Reference Voltage for
VREF0, VREF1
I
REFx = ±0.5mA
(VDD/2) – 0.15
VDD/2
(VDD/2) + 0.15
Input Bias
fREF < 1.5GHz
fREF > 1.5GHz
0.1
0.2
1.5
1.5
V
V
VPP
Peak-to-Peak Voltage1
Common Mode Input
Voltage1, 2
VCMR
1.0
V
DD – (VPP/2)
V
NOTE 1: VIL should not be less than -0.3V. VIH should not be greater than VDD
NOTE 2: Common mode input voltage is defined at the crosspoint.
.
Table 4D. LVDS DC Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
Outputs Loaded with 100
247
VOD
VOS
50
1.125
1.375
50
VOS
VOS Magnitude Change
mV
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8SLVD1212 Datasheet
AC Electrical Characteristics
1
Table 5. AC Electrical Characteristics, V = 2.5V ± 5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input
PCLK[0:1],
fREF
2
GHz
Frequency nPCLK[0:1]
Input PCLK[0:1],
V/t
1.5
V/ns
ps
Edge Rate nPCLK[0:1]
Propagation Delay2
PCKx, nPCLKx to any Qx, nQx
for VPP = 0.1V or 0.3V
tPD
200
310
500
tsk(o)
tsk(p)
tsk(pp)
Output Skew3, 4
Pulse Skew5, 6
45
80
ps
ps
ps
fREF = 100MHz, 500MHz, 1GHz, 1.5GHz
Part-to-Part Skew4, 7
300
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
f
REF = 156.25MHz, VPP = 1.0V, VCMR = 1V
Integration Range: 10kHz – 20MHz
tJIT
77
90
fs
20% to 80%
tR / tF
Output Rise/ Fall Time
100
75
200
ps
Outputs Loaded with 100
MUXISOLATION Mux Isolation8
f
REF = 100MHz
dB
NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Output pulse skew tsk(p) is absolute difference of the propagation delay times: |tPLH - tPHL|.
NOTE 6: Output duty cycle is frequency dependent: odc= input duty cycle +/- ((tsk(p)/2)*(1/output period))*100.
NOTE 7: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 8: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter 77fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
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8SLVD1212 Datasheet
Parameter Measurement Information
V
DD
nPCLK[0:1]
PCLK[0:1]
V
DD
VPP
Cross Points
VCMR
GND
2.5V LVDS Output Load Test Circuit
Differential Input Level
nPCLK[0:1]
PCLK[0:1]
nQx
Qx
nQy
nQy
Qy
Qy
tPLH
tPHL
tsk(p)= |tPHL - tPLH
|
Pulse Skew
Output Skew
Part 1
nQx
nQ[0:11]
80%
80%
Qx
VOD
20%
Part 2
20%
nQy
Q[0:11]
tF
tR
Qy
tsk(pp)
Part-to-Part Skew
Output Rise/Fall Time
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Parameter Measurement Information, continued
Spectrum of Output Signal Q
MUX selects active
input clock signal
A0
A1
nPCLK[0:1]
PCLK[0:1]
MUX_ISOLATION = A0 – A1
nQ[0:11]
MUX selects other input
Q[0:11]
tPD
ƒ
Frequency
(fundamental)
Propagation Delay
MUX Isolation
Differential Output Voltage Setup
Offset Voltage Setup
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8SLVD1212 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVDS Outputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from PCLK to
ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V1 in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 2.5V,
R1 and R2 value should be adjusted to set V1 at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Suggested edge
rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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8SLVD1212 Datasheet
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figure 2A to Figure 2E show interface examples for
the PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
CML
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver
Figure 2D. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
2.5V
2.5V
PCLK
PCLK
nPCLK
nPCLK
LVPECL
CML Built-In Pullup
Input
Figure 2B. Figure 2C.PCLK/nPCLK Input Driven by a
Figure 2E. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
2.5V LVDS Driver
2.5V
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
LVPECL
Figure 2C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
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8SLVD1212 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
LVDS
Driver
LVDS
ZT
Receiver
Figure 3A. Standard LVDS Termination
Z
T
2
ZO ZT
LVDS
LVDS
Driver
Receiver
C
Z
T
2
Figure 3B. Optional LVDS Termination
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8SLVD1212 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
SOLDER
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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8SLVD1212 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8SLVD1212I. Equations and example calculations are
also provided.
1. Power Dissipation.
The total power dissipation for the 8SLVD1212I is the sum of the core power plus the output power dissipation due to the load. The following
is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
The maximum current at 85°C is as follows:
IDD_MAX = 213mA
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 213mA = 559.125mW
Total Power_MAX = 559.125mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 33°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.559W * 33°C/W = 103.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance for 40-Lead VFQFN, Forced Convection
JA
JA (°C/W) vs. Air Flow (m/s)
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
33°C/W
26.3°C/W
24°C/W
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8SLVD1212 Datasheet
Reliability Information
Table 7. vs. Air Flow Table for a 40-Lead VFQFN, Forced Convection
JA
JA (°C/W) vs. Air Flow (m/s)
Meters per Second
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
33°C/W
26.3°C/W
24°C/W
Transistor Count
The transistor count for the 8SLVD1212 is: 8301
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8SLVD1212 Datasheet
40-Lead VFQFN Package Outline and Package Dimensions
Table 8. Package Dimensions for 40-Lead Package
DIMENSIONS
NOTES:
The drawing and dimension data originates from IDT Package
Outline Drawing PSC-4115, Rev 07.
1. Dimensions and tolerances conform to ASME Y14.5M-1994.
SYMBOL
MIN
NOM
MAX
NOTE
2. N is the number of terminals.
b
0.18
0.25
0.3
4
Nd is the number of terminals in X-direction.
Ne is the number of terminals in Y-direction.
D
6.00 BSC
6.00 BSC
4.65
3. All dimensions are in millimeters.
E
4. Dimension b applies to plated terminal and is measured
between 0.20 and 0.30mm from terminal tip.
D2
4.50
4.50
0.30
4.75
4.75
0.50
5. The Pin #1 identifier must exist on the top surface of the
package by using indentation mark or other feature of package
body.
E2
4.65
L
0.40
6. Exact shape and size of this feature is optional.
7. Applied to exposed pad and terminals. Exclude embedded part
of exposed pad from measuring.
e
0.50 BSC
40
N
2
7
2
8. Applied only for terminals.
9. This outline conforms to JEDEC Publication 95, Registration
MO-220, Variation VJJD-5 with exception of D2 & E2.
A
A1
0.80
0.00
0.90
1.00
0.05
0.02
A3
0.2 REF
10
Nd and Ne
©2016 Integrated Device Technology, Inc.
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Revision 3, July 5, 2016
8SLVD1212 Datasheet
Recommended Land Pattern
NOTES:
The Recommended Land Pattern originates from IDT Package
Outline Drawing PSC-4115, Rev 07.
1. All dimensions are in millimeters. Angles in degrees.
2. Top down view, as viewed on PCB.
3. Component outline shows for reference in green.
4. Land pattern in blue, NSMD pattern assumed.
5. Land pattern recommendation per IPC-7351B generic
requirement for surface mount design and land pattern.
©2016 Integrated Device Technology, Inc.
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Revision 3, July 5, 2016
8SLVD1212 Datasheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8SLVD1212NLGI
IDT8SLVD1212NLGI
40-Lead VFQFN, Lead-Free
Tray
-40°C to 85°C
Tape & Reel,
pin 1 orientation:
EIA-481-C
8SLVD1212NLGI8
IDT8SLVD1212NLGI
40-Lead VFQFN, Lead-Free
40-Lead VFQFN, Lead-Free
-40°C to 85°C
-40°C to 85°C
Tape & Reel,
pin 1 orientation:
EIA-481-D
8SLVD1212NLGI/W
IDT8SLVD1212NLGI
Table 10. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Correct Pin 1 ORIENTATION
8
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Correct Pin 1 ORIENTATION
/W
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
©2016 Integrated Device Technology, Inc.
19
Revision 3, July 5, 2016
8SLVD1212 Datasheet
Revision History Sheet
Rev
Table
Page
17 - 18
15
Description of Change
Date
2
Corrected package drawings.
08/21/15
T6
T7
Thermal Resistance table description, corrected the word “Convection”, updated table
header.
3
7/5/16
16
Reliability table description, added “Forced Convection”, updated table header.
Updated datasheet header/footer.
©2016 Integrated Device Technology, Inc.
20
Revision 3, July 5, 2016
8SLVD1212 Datasheet
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and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
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