9248AG-92LF [IDT]
Processor Specific Clock Generator, 100MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, TSSOP-48;
| 型号： | 9248AG-92LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 100MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, GREEN, TSSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9248-92
Systems, Inc.
TM
Mobile Pentium II System Clock Chip
RecommendedApplication:
Features
The ICS9248-92 is a fully compliant timing solution for the
•
•
•
Generates system clocks for CPU, SDRAM, PCI, plus
14.318MHz REF(0:2), USB, PlusSuperI/O
I2C serial configuration interface provides output clock
disabling and other functions
Intel mobile 440BX/MX chipset requirements.
GeneralDescription:
FeaturesincludetwostrongCPU, sevenPCIandeightSDRAM
clocks. Three reference outputs are available equal to the
crystal frequency. Stronger drive CPUCLK outputs typically
provide greater than 1 V/ns slew rate into 20pF loads. This
device meets rise and fall requirements with 2 loads per CPU
output (ie, one clock to CPU and NB chipset, one clock to two
L2 cache inputs).
MODE input pin selects optional power management
input control pins
•
•
•
•
•
•
•
Two fixed outputs separately selectable as 24 or 48MHz
2.5Voutputs:CPU
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz
No power supply sequence requirements
Usesexternal14.318MHzcrystal
48pin240milTSSOPpackage
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:1) clocks and PCI_STOP# will
stopPCICLK(0:5)clocks
Output enable register
for serial port control:
1 = enable
0 = disable
PCICLK outputs typically provide better than 1V/ns slew rate
into30pFloadswhilemaintaining50±5%dutycycle. TheREF
clock outputs typically provide better than 0.5V/ns slew rates.
The ICS9248-92 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Pin Configuration
Block Diagram
48-Pin TSSOP 240 mil Package
Functionality
Crystal(X1, X2)=14.31818MHz
SEL
100/66#
CPUCLK
(MHz)
PCICLK
(MHz)
0
66.6
33.3
1
100
33.3
Pentium is a trademark on Intel Corporation.
9248-92RevE02/21/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-92
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
45, 1, 2
REF [2:0]
OUT
Reference clock Output
3, 10, 17, 24,
31, 37, 43
4
GND
X1
PWR
IN
Ground (common)
Crystal or reference input, has internal crystal load cap
Crystal output, has internal load cap and feedback
resistor to X1
5
X2
OUT
6
MODE
VDDPCI
IN
Input function selection (see table page 3)
Supply for PCICLK_F, PCICLK [0:5], nominal 3.3V
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
7, 15
PWR
OUT
OUT
8
PCICLK_F
PCICLK [0:5]
9, 11, 12, 13, 14, 16
Selects 66.6MHz or 100MHz for SDRAM and CPU
(see tables page 1, 3)
18
SEL100/66#
IN
19
20
21
22
SDATA
SCLK
IN
IN
I2C data input
I2C clock input
VDD48
PWR
OUT
Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V
48/24MHz driver output for USB or Super I/O
48/24MHzA
23
25
48/24MHzB
OUT
48/24MHz driver output for USB or Super I/O
VDDCOR
SDRAM7
PWR
OUT
IN
Supply for PLL core, nominal 3.3V
SDRAM clock output, fanout buffer output from BUF_IN pin
Halts PCI Bus [0:5] at logic "0" level when low
SDRAM clock output, fanout buffer output from BUF_IN pin
Halts CPU clocks at logic "0" level when low
26
PCI_STOP#
SDRAM6
OUT
IN
27
CPU_STOP#
Supply for SDRAM [0:5], SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#, nominal 3.3V
28, 34
VDDSDR
PWR
40
VDDLCPU
PWR
OUT
Supply for CPUCLK [0:1] 2.5V nominal
42, 41
CPUCLK [0:1]
CPUCLK clock output, powered by VDDL2
SDRAM clock outputs, fanout buffer outputs from
BUF_IN pin
36, 35, 33, 32, 30, 29
SDRAM [0:5]
OUT
38
39
FB
OUT
IN
Feedback out
BUF_IN
Input for SDRAM buffers
When driven active (low) powers down the device into low
power state. Internal clocks are disabled, VCO and crystal
OSC are stopped.
44
PWR_DWN#
VDDREF
IN
48, 46
PWR
Supply for REF [0:2], X1, X2, nominal 3.3V
Power Groups
VDDCOR=SupplyforPLLcore
VDDREF=REF[0:2],X1,X2
VDDPCI=PCICLK_F,PCICLK[0:5]
VDDSDR=SDRAM[0:7]
VDD48=48/24MHzA,48/24MHz
VDDLCPU=CPUCLK[0:1]
2
ICS9248-92
Power-On Conditions
SEL
100/66.6#
MODE
PIN #
41, 42
16, 14, 13, 12,
11, 9, 8
41, 42
16, 14, 13, 12,
11, 9, 8
DESCRIPTION
CPUCLKs
PCICLKs
FUNCTION
100 MHz - w/serial config enable/disable
33.3 MHz - w/serial config enable/disable
66.6 MHz - w/serial config enable/disable
33.3 MHz - w/serial config enable/disable
1
1
CPUCLKs
PCICLKs
0
1
1
0
Power Management, PCI [0:5] Clocks
Stopped when low
Power Management, CPU [0:5] Clocks
Stopped when low
33.3 MHz - PCI Clock Free running
100 MHz - CPU Clocks w/external Stop Control and serial
config individual enable/disable.
26
PCI_STOP#
27
8
CPU_STOP#
PCICLK_F
CPUCLKs
41, 42
16, 14, 13, 12,
11, 9
33.3 MHz - PCI Clocks w/external Stop control and serial
config individual enable/disable.
PCICLKs
Power Management, PCI [0:5] Clocks
Stopped when low
26
PCI_STOP#
Power Management, CPU [0:5] Clocks
Stopped when low
33.3 MHz - PCI Clock Free running for Power Management
66.6 MHz - CPU Clocks w/external Stop control and serial
config individual enable/disable.
27
8
CPU_STOP#
PCICLK_F
CPUCLKs
0
0
41, 42
16, 14, 13, 12,
11, 9
33.3 MHz - PCI Clocks w/external Stop control and serial
config individual enable/disable.
PCICLKs
Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then produced
are on the MODE pin as shown in the table below.
CLOCK
REF (0:2)
48/24 MHz
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
48 MHz
3
ICS9248-92
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controler (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
4
ICS9248-92
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0)
(default on Bits 3, 2 = 1)
Note: PWD=Power-UpDefault
BIT
Bit 7
Bit 6
PIN#
-
-
DESCRIPTION
PWD
0
0
Reserved
Reserved
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
In Spread Spectrum, Controls Spreading
(0= 0.5% 1= 0.25%)
Bit 5
Bit 4
-
1
0
Bit 3
Bit 2
23
22
48/24 MHz (Frequency Select) 1=48 MHz, 0=24 MHz
48/24 MHz (Frequency Select) 1=48 MHz, 0=24 MHz
1
1
Bit1
Bit0
1
1
0
0
1 - Tri-State
0 - Spread Spectrum Enable
1 - Testmode
Bit 1
Bit 0
-
10
0 - Normal operation
Select Functions
PCI,
24 MHz
Selection
48 MHz
Selection
Functionality
CPU
SDRAM
PCI_F
REF
Tristate
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
Testmode
TCLK/21
TCLK/41
TCLK/21
TCLK1
TCLK/41
TCLK/21
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
5
ICS9248-92
Byte 2: PCICLK Clock Register
Byte 1: CPU, 24/48 MHz Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
PWD
DESCRIPTION
48/24 MHz (Act/Inact)
48/24 MHz (Act/Inact)
Reserved
-
1
1
1
1
1
1
1
1
Reserved
23
22
-
1
1
1
1
1
1
1
1
8
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
16
14
13
12
11
9
-
Reserved
-
Reserved
-
Reserved
41
42
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4: SDRAM Clock Register
Byte 3: SDRAM Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1(Act/Inact)
SDRAM0 (Act/Inact)
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
26
27
29
30
32
33
35
36
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 5: Peripheral Clock Register
Byte6:OptionalRegisterforFuture
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
-
-
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Reserved
-
Reserved
-
Reserved
45
1
2
REF2 (Act/Inact)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes:
PWD = Power-Up Default
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Note: PWD=Power-UpDefault
6
ICS9248-92
Power Management
Clock Enable Configuration
Other Clocks,
SDRAM,
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK
REF,
Crystal
VCOs
48/24 MHz A
48/24 MHz B
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Stopped
Running
Running
Running
Running
Off
Off
Running
Running
Running
Running
Running
Running
Running
Running
Low
33.3 MHz
Low
100/66.6 MHz
100/66.6 MHz
33.3 MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-92PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1
1
1
PCI_STOP#
1 (Enabled)1
1
PWR_DWN#
1 (Normal Operation)3
0 (Power Down)4
3mS
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF will be stopped independant of these.
7
ICS9248-92
CPU_STOP#Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-92. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled.The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS9248-92.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP#Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-92. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP#issynchronizedbytheICS9248-92 internally.TheminimumthatthePCICLK(0:5)clocksareenabled(PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawing shown on next page.)
8
ICS9248-92
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PD#Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the ICS9248-92 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on
latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
9
ICS9248-92
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% VDDL = 2.5V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
0.8
V
V
VIL
VSS-0.3
IDD
77
2.8
180
mA
mA
MHz
pF
Supply Current
Input frequency
CL = 0 pF; Select @ 66M
25
IDDL2.5
Fi
VDD = 3.3 V;
14.318
CIN
CINX
Logic Inputs
5
45
3
Input Capacitance1
X1 & X2 pins
27
36
ps
Transition Time1
Clk Stabilization1
Skew1
Ttrans
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
1.5
ms
ms
ns
TSTAB
TCPU-PCI
3
1.5
2.2
4.0
VTP CI = 1.5 V; VTCP U = 1.25 V
1Guarenteed by design, not 100% tested in production.
10
ICS9248-92
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Period
SYMBOL
CONDITIONS
MIN
10
TYP
10
MAX
UNITS
ns
period(norm) VT = 1.25 V; 100MHz
10.5
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
VOH2B
VOL2B
IOH2B
IOL2B
IOH = -12.0 mA
IOL = 12 mA
1.8
2.3
V
0.31
0.4
-27
V
VOH = 1.7 V
mA
mA
VOL = 0.7 V
27
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
55
ns
ns
%
1
Fall Time
tf2B
1
1
Duty Cycle
dt2B
50
1
Skew
tsk2B
VT = 1.25 V
30
95
ps
ps
1
tcyc-cyc
VT = 1.25 V
Jitter
186
250
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz,24MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2
TYP
3.21
0.21
MAX UNITS
V
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
IOH5
IOL5
tr5
tf5
dt5
tjabs5
tjabs5
0.4
-23
V
mA
mA
29
1
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V, REF
VT = 1.5 V, 48 MHz
2.5
2.5
52
385
469
4
4
55
800
800
ns
ns
%
ps
ps
Fall Time1
Duty Cycle1
45
Jitter, Absolute1
Jitter, Absolute1
1Guaranteed by design, not 100% tested in production.
11
ICS9248-92
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH1
VOL1
CONDITIONS
MIN
2.1
TYP
3.3
0.17
MAX UNITS
V
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-24
V
mA
mA
IOH1
IOL1
30
0.5
0.5
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.6
1.8
50
2
2
ns
ns
%
dt1
tsk1
55
500
VT = 1.5 V
222
ps
Jitter, Absolute1
tjabs1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
-250
250
500
ps
ps
Jitter, Cycle-to-cycle1
227
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.2
TYP
3.18
0.35
-74
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
IOH1
IOL1
tr1
tf1
dt1
tsk1
tp1
0.4
-46
V
mA
mA
54
0.5
0.5
45
Rise Time1
Fall Time1
VOL = 0.8 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.54
1.51
51
200
3.5
1.6
1.6
55
250
5
ns
ns
%
ps
ns
Duty Cycle1
Skew1
VT = 1.5 V
VT = 1.5 V
Propagation Delay1
1
1Guaranteed by design, not 100% tested in production.
12
ICS9248-92
GeneralLayoutPrecautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
Ferrite
Bead
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
1
2
48
3.3V Power Route
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
C1
C1
4
Notes:
5
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in all
places to improve readability of
diagram.
2
6
1
C4
Clock Load
7
8
2.5V Power Route
9
C3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2 Optional crystal load capacitors are
recommended. They should be
includedinthelayoutbutnotinserted
unless needed.
Component Values:
3.3V Power Route
C1 : Crystal load values determined by user
C2: 22 F/20V/Dcase/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB=Fair-Riteproducts2512066017X1
Allunmarkedcapacitorsare0.01 Fceramic
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
ConnectionstoVDD:
= Clock Load
13
ICS9248-92
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
MIN
MAX
MIN
.488
MAX
(240 mil)
48
12.40
12.60
.496
7/6/00 Rev B
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS9248yG-92
Example:
ICS XXXX y G - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
RevisionDesignator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
14
information being relied upon by the customer is current and accurate.
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9248-92 (Notebook Chipsets)
Description
The ICS9248-92 is a fully compliant timing solution for the Intel mobile 440BX/MX chipset requirements.
Market Group
PC CLOCK
Additional Info
General Description: Features include two strong CPU, seven PCI and eight SDRAM clocks. Three reference outputs are available equal to the
crystal frequency. Stronger drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. This device meets rise and fall
requirements with 2 loads per CPU output (ie, one clock to CPU and NB chipset, one clock to two L2 cache inputs).
Related Orderable Parts
Attributes
9248AG-92
9248AG-92LF
9248AG-92LFT
9248AG-92T
3.3 V (PA48)
3.3 V (PAG48)
3.3 V (PAG48)
3.3 V (PA48)
TSSOP 48
NA
Voltage
Package
Speed
TSSOP 48
TSSOP 48
TSSOP 48
NA
NA
C
NA
C
C
C
Temperature
Active
No
Active
Yes
76
Active
No
Active
No
Status
Sample
76
1000
1000
1000
Minimum Order Quantity
Factory Order Increment
38
38
1000
Related Documents
Type
Title
Size
Revision Date
Datasheet
9248-92 Datasheet
9248-92 IBIS Model
342 KB
166 KB
03/24/2006
03/24/2006
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