ICS507-01-DWFLF [IDT]
Clock Generator, 200MHz, CMOS, DIE;
| 型号： | ICS507-01-DWFLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 200MHz, CMOS, DIE |
| 文件： | 总5页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS507-01
PECL Clock Synthesizer
Description
Features
• Packaged as 16 pin narrow SOIC
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 5 - 52 MHz
• Enable usage of common low-cost crystal
• Differential PECL output clock frequencies up
to 200 MHz
The ICS507-01 is an inexpensive, simple way
to generate a low jitter 155.52 MHz (or other high
speed) differential PECL clock output from a low
frequency crystal input. Using Phase-Locked-Loop
(PLL) techniques, the devices use a standard
fundamental mode crystal to produce output clocks up
to 200 MHz.
• Duty cycle of 49/51
Stored in each chip’s ROM is the ability to generate a
selection of different multiples of the input reference
frequency, including an exact 155.52 MHz clock from
common crystals. For lowest jitter and phase noise on
a 155.52 MHz clock, a 19.44 MHz crystal and the x8
selection can be used.
• Operation voltage of 3.3 V or 5.0 V (±5%)
• Ideal for SONET applications and oscillator
manufacturers
• Available in die form
• Industrial temperature versions available
• ICS507-02 is no longer available
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
Block Diagram
1.1kW
GND
VDD
RES
270
W
Output
Buffer
2
PECL
S0:1
Clock Synthesis
and
Control Circuitry
62W
VDD
Crystal
or
clock
X1
Clock
Buffer/
Crystal
62W
Output
Buffer
PECL
Oscillator
X2
270W
Output Enable
(both outputs)
Output resistor values shown are for unterminated lines. Refer to MAN09 for additional information.
MDS 507 H
1
Revision 092503
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01
PECL Clock Synthesizer
Clock Multiplier Select Table
Pin Assignment
*For ICS 507-01 or ICS507-02
at 3.3V, use this selection to get
155.52 MHz from a 16 MHz
input.
S1
0
S0
0
Multiplier
9.72X*
10X
16
15
14
13
12
11
10
9
X2
1
2
3
4
5
6
7
8
X1/ICLK
VDD
0
M
1
NC
0
12X
S0
VDD
S1
M
M
M
1
0
6.25X
8X
OE
M
1
For lowest phase noise
generation of 155.52 MHz, use
a 19.44 MHz crystal and the 8X
selection.
5X
NC
GND
GND
NC
0
2X
NC
1
M
1
3X
RES
PECL
1
4X
PECL
0 = connect pin directly to ground
1 = connect pin directly to VDD
M = leave unconnected (floating)
16 pin narrow (150 mil) SOIC
Pin Descriptions
Number Name
Type Description
1
2
X1/ICLK
VDD
VDD
S1
XI
P
P
TI
P
P
-
Crystal or clock connection. Connect to a fundamental parallel mode crystal, or clock.
VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3.
VDD. Connect to VDD on pin 2. Decouple with pin 5.
Multiplier select pin 1. Determines output frequency per table above.
Connect to ground.
3
4
5
GND
GND
NC
6
Connect to ground.
7
No connect. No internal connection.
8
PECL
PECL
RES
NC
O
O
I
PECL Output. Connect to resistor load as shown on page one.
Complementary PECL Output. Connect to resistor load as shown on page one.
Bias Resistor Input. Connect a resistor between this pin and VDD.
No connect. No internal connection.
9
10
11
12
13
14
15
16
-
NC
-
No connect. No internal connection.
OE
I
Output Enable. Tri-states both outputs when low. Internal pull-up.
Multiplier select pin 0. Determines output frequency per table above.
No connect. No internal connection.
S0
TI
-
NC
X2
XO Crystal connection. Connect to crystal, or leave unconnected for clock input.
Key: I=Input, O=output, TI=tri-level input, P=power supply connection; XI, XO=crystal connections
MDS 507 H
2
Revision 092503
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01
PECL Clock Synthesizer
Electrical Specifications
Parameter
Conditions
Minimum Typical Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
ICS507M-0x
7
VDD+0.5
VDD+0.5
70
V
-0.5
-0.5
0
V
Clock Output
V
Ambient Operating Temperature
°C
°C
°C
°C
ICS507M-0xI
-40
85
Soldering Temperature
Storage temperature
Max of 20 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted)
Operating Voltage, VDD
Input High Voltage, VIH
3.0
5.5
V
V
ICLK only
ICLK only
S0, S1
VDD/2 + 1
VDD/2
VDD/2
Input Low Voltage, VIL
VDD/2-1
0.5
V
Input High Voltage, VIH
VDD-0.5
VDD-1.2
V
Input Low Voltage, VIL
S0, S1
V
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Supply Current, note 3
Internal Crystal Capacitance, X1 and X2
Input Capacitance
Note 2
V
Note 2
VDD-2.0
V
No Load, 155.52MHz
Pins 1, 8
S0, S1
63
mA
pF
pF
0
5
AC CHARACTERISTICS (VDD = 3.3, 5.0 V unless otherwise noted)
Input Crystal Frequency
Input Clock Frequency
Output Frequency, ICS507-01
5
27
MHz
MHz
MHz
MHz
MHz
5
52
0 to 70°C VDD = 5.0 V
0 to 70°C VDD = 3.3 V
10
10
10
200
156
125
Output Frequency, ICS507-01I
-40 to 85°C VDD = 3.3 V or 5.0 V
Output Clock Duty Cycle
PLL Bandwidth
48
10
52
%
kHz
ps
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Deviation from mean
±75
20
ps
Notes: 1) All typical values are at 5.0 V and 25°C unless otherwise noted.
2) VOH and VOL can be set by the external resistor values on the PECL outputs.
3) IDD includes the current through the external resistors, which can be modified.
4) The phase relationship between input and output can change at power up. For a fixed phase
relationship, see one of the ICS zero delay buffers.
5) Except S1=0, S0=0 setting (This setting specific to 16 MHz in, 155.52 MHz out).
6) The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the following equation, where CL
is the specified crystal load capacitance: Crystal caps (pF) = (CL-5)x2. So, for a crystal with 16 pF load capacitance, use two 22 pF caps.
MDS 507 H
3
Revision 92503
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01
PECL Clock Synthesizer
Applications
High Frequency Differential PECL Oscillators: The ICS507 plus a low frequency, fundamental mode crystal
can build a high frequency differential output oscillator. For example, a 10 MHz crystal connected to the ICS507 with
the 12X output selected (S1=0, S0=1) produces a 120 MHz PECL output clock.
High Frequency TCXO: Extending the previous application, an inexpensive, low frequency TCXO can be built
and the output frequency can be multiplied using the ICS507. Since the output of the chip is phase-locked to the
input, the ICS507 has no temperature dependence, and the temperature coefficient of the combined system is the
same as that of the low frequency TCXO.
High Frequency VCXO: The bandwidth of the PLL is guaranteed to be greater than 10 kHz. This means that the
PLL will track any modulation on the input with a frequency of less than 10 kHz. By using this property, a low
frequency VCXO can be built, and the output can then be multiplied with the ICS507 to give a high frequency output,
thereby producing a high frequency VCXO.
Decoupling and External Components
The ICS507 requires a 0.01µF decoupling capacitor to be connected between VDD and GND on pins 2 and 5. It
must be connected close to the ICS507. Other VDD and GND connections should be connected to those pins, or
to the VDD and GND planes on the board. A resistor must be connected between the RES (pin 10) and VDD.
Another four resistors are needed for the PECL outputs as shown on the block diagram on page 1. Suggested
values of these resistors are shown in the Block Diagram, but they can be varied to change the differential pair
output swing, and the DC level; refer to MAN09.
MDS 507 H
4
Revision 092503
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01
PECL Clock Synthesizer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Inches
Millimeters
Min Max
Symbol
Min
Max
A
A1
B
0.0532 0.0688 1.35
0.0040 0.0098 0.10
0.0130 0.0200 0.33
0.0075 0.0098 0.19
1.75
0.24
0.51
0.24
E
H
C
D
E
INDEX
AREA
0.3859 0.3937 9.80 10.00
0.1497 0.1574 3.80
4.00
e
.050 BSC
1.27 BSC
1
2
H
h
0.2284 0.2440 5.80
0.0099 0.0195 0.25
0.0160 0.0500 0.41
6.20
0.50
1.27
h x 45°
L
D
A
L
A1
C
B
e
Ordering Information
Part/Order Number
Marking
Package
Temperature Minimum
Quantities
ICS507M-01
ICS507M-01T
ICS507M-01I
ICS507M-01
ICS507M-01
16 pin narrow SOIC
16 pin SOIC on tape and reel
16 pin narrow SOIC
0 to 70°C
0 to 70°C
-40 to 85°C
-40 to 85°C
0 to 70°C
0 to 70°C
0 to 70°C
-
2500 pieces
-
ICS507M-01I
ICS507M-01IT
ICS507-01-DSW
ICS507-01-DPK
ICS507-01-DWF
ICS507M-01I
16 pin SOIC on tape and reel
Probed wafers, cut, on sticky tape
Tested die in waffle pack
2500 pieces
1 wafer
-
-
-
1000 pieces
1 wafer
Die on uncut, probed wafers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits,
patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring
extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 507 H
5
Revision 092503
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
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