ICS840245AGILF [IDT]
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16;
| 型号： | ICS840245AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 光电二极管 |
| 文件： | 总14页 (文件大小：650K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ICS840245I
GENERAL DESCRIPTION
FEATURES
• Five LVCMOS outputs, 15Ω typical output impedance
The ICS840245I is a low skew, 1-to-5 LVCMOS/
ICS
LVTTL SATA/SAS Clock Generator and is a mem-
ber of the HiPerClocksTM family of high performance
clock solutions from IDT. The ICS840245I can syn-
thesize 75MHz reference clock frequencies with a
• Crystal oscillator interface
HiPerClockS™
• Supports the following output frequency: 75MHz
• Output skew: 25ps (typical)
25MHz crystal. Each of the 5 outputs on the ICS840245I can
drive two series terminated 50Ω transmission lines, effectively
making the ICS840245I a 1-to-10 clock generator. An output
enable (OE) pin, which controls only the Q4 output, allows the
application to use Q4 as an optional output (for example, test
output pin). The ICS840245I uses IDT’s 3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical
random rms phase jitter. The ICS840245I is packaged in a
16-pin TSSOP package.
• RMS phase jitter @ 75MHz (900kHz - 7.5MHz):
0.454ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
1
2
3
4
5
6
7
8
Pullup
XTAL_OUT
XTAL_IN
VDDA
OE
VDD
GND
PLL_SEL
GND
16
15
14
13
12
11
10
9
VDDO
Q0
Q1
GND
Q2
Q3
PLL_SEL
Q1
Q2
0
25MHz
XTAL_IN
Phase
Detector
VCO
600MHz
OSC
1
N = 8
Q3
Q4
VDDO
Q4
XTAL_OUT
M = 24
(fixed)
ICS840245I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
Pullup
OE
G Package
Top View
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245I
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1,
2
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface.
3
VDDA
Power
Analog supply pin.
Output clock enable pin. When HIGH, Q4 output is enabled.
When LOW, forces Q4 to Hi-Z state. LVCMOS/LVTTL interface levels.
See Table 3A.
4
OE
Input
Pullup
Pullup
5
VDD
Power
Power
Core supply pin.
6, 8, 13
GND
Power supply ground.
PLL select pin. Selects between PLL and bypass mode. When HIGH,
PLL is enabled. LVCMOS/LVTTL interface levels. See Table 3B.
7
PLL_SEL
Input
9, 11, 12,
14, 15
Q4, Q3, Q2,
Q1, Q0
Output
Power
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pins.
10, 16
VDDO
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
8
RPULLUP
51
15
20
3.3V 5%
2.5V 5%
ROUT
Output Impedance
Ω
TABLE 3A. CONTROL FUNCTION TABLE
Control Input
Output
Q0
OE
0
Hi-Z
1
Active
TABLE 3B. PLL_SEL FUNCTION TABLE
Control Input
Outputs
Q0:Q4
Bypass
PLL
PLL_SEL
0
1
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
ICS840245I
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
3.465
48
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.08
3.135
3.3
3.3
V
mA
mA
mA
IDDA
IDDO
8
No Load
36
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
2.625
48
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.12
2.375
3.3
2.5
V
mA
mA
mA
IDDA
IDDO
12
No Load
32
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
VDD
2.625
43
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.12
2.375
2.5
2.5
V
mA
mA
mA
IDDA
IDDO
12
No Load
32
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
VDD = 3.3V
V
Input Low Voltage
VDD = 2.5V
0.7
V
IIH
IIL
Input High Current OE, PLL_SEL
Input Low Current OE, PLL_SEL
VDD = VIN = 3.465V or 2.625V
5
µA
VDD = 3.465V or 2.625V,
-150
µA
VIN = 0V
V
DDO = 3.3V 5%
VDDO = 2.5V 5%
VDDO = 3.3V 5% or 2.5V 5%
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pf parallel resonant crystal.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
75
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
55
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
Integration Range: 900kHz - 7.5MHz
20% to 80%
0.503
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
49
600
51
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
75
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
55
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
Integration Range: 900kHz - 7.5MHz
20% to 80%
0.494
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
250
49
600
51
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
75
MHz
ps
tsk(o)
Output Skew; NOTE 1, 3
50
RMS Phase Jitter (Random);
NOTE 2
tjit(Ø)
Integration Range: 900kHz - 7.5MHz
20% to 80%
0.454
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
49
600
51
ps
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 75MHZ @ 3.3V
0
-10
-20
75MHz
RMS Phase Jitter (Random)
-30
-40
-50
-60
-70
-80
-90
900kHz to 7.5MHz = 0.503ps (typical)
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 75MHZ @ 2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
75MHz
RMS Phase Jitter (Random)
900kHz to 7.5MHz = 0.454ps (typical)
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.05V 5%
1.65V 5%
1.25V 5%
1.65V 5%
2.05V 5%
VDD,
VDDO
SCOPE
VDD
SCOPE
VDDA
VDDO
Qx
LVCMOS
GND
Qx
VDDA
LVCMOS
GND
-1.65V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5%
1.25V 5%
VDDO
SCOPE
VDD,
VDDO
Qx
Qy
2
VDDA
Qx
LVCMOS
GND
VDDO
2
tsk(o)
-1.25V 5%
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
VDDO
2
Q0:Q4
tPW
tPERIOD
tPW
Offset Frequency
x 100%
odc =
f1
f2
tPERIOD
RMS Jitter = Area Under Offset Frequency Markers
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
tF
80%
tR
20%
20%
Clock
Outputs
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840245I provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V or 2.5V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. There should be
no trace attached.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS840245I has been characterized with 18pF parallel
resonant crystals.The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
C2
33p
XTAL_OUT
XTAL_IN
X1
18pF Parallel Crystal
C1
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
ICS840245I
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840245I is: 1965
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
ICS840245I
FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS840245AGI
Marking
840245AI
840245AI
40245AIL
40245AIL
Package
Shipping Packaging Temperature
16 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS840245AGIT
ICS840245AGILF
ICS840245AGILFT
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
T4A
Page
3
3
Description of Change
Power Supply 3.3V DC Characteristics Table - changed IDD max. from 41mA to 48mA.
Date
T4B
Power Supply 3.3/2.5V DC Characteristics Table - changed IDD max. from 40mA to
48mA, IDDA max. from 8mA to 12mA, IDDO from 27mA to 32mA, and VDDA min. from
V
DD - 0.08V to VDD - 0.12V.
Power Supply 2.5V DC Characteristics Table - changed IDD max. from 38mA to 43mA,
DDA max. from 8mA to 12mA, IDDO from 27mA to 32mA, and VDDA min. from
B
11/16/06
T4C
3
9
I
- 0.08V to VDD - 0.12V.
Corrected Crystal Input Interface drawing.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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ICS840245AGI REV. B NOVEMBER 16, 2006
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FEMTOCLOCKS™ 1:5, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
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+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
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trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
ICS840245AGILFT
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
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