ICS84324DMT [IDT]
Clock Generator, 125MHz, PDSO24, 0.300 INCH, MS-013, MO-119, SOIC-24;
| 型号： | ICS84324DMT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 125MHz, PDSO24, 0.300 INCH, MS-013, MO-119, SOIC-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84324 is a Crystal-to-3.3V LVPECL Fre- • 6 differential 3.3V LVPECLoutputs
,&6
quency Synthesizer with Fanout Buffer and a mem-
ber of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. Output frequency can
be programmed using the feedback and output fre-
• Crystal oscillator interface
HiPerClockS™
• Output frequency range: 53.125MHz to 125MHz
• Crystal input frequency: 25MHz
• Cycle-to-cycle jitter: 25ps (typical)
quency select pins. The low phase noise characteristics of the
ICS84324 make it an ideal clock source for Fibre Channel 1 and
Gigabit Ethernet applications.
• RMS phase jitter at 106.25MHz, using a 25MHz crystal
(637KHz to 10Mhz): 4.15ps
FUNCTION TABLE
• Typical Phase noise at 106.25MHz
Offset
Noise Power
Inputs
Output Frequency
F_OUT
100Hz ..................-80dBc/Hz
1KHz ................ -105dBc/Hz
10KHz ................ -125dBc/Hz
100KHz ................ -125dBc/Hz
MR F_SEL1 F_SEL0
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
LOW
53.125MHz
106.25MHz
62.5MHz
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial termperature information available upon request
125MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
24
23
22
VCC
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
VEE
XTAL1
OSC
XTAL2
6
Q0:Q5
21
20
19
18
17
16
15
14
13
0
/
Output
Divider
5
6
7
6
/
nQ0:nQ5
1
PLL
8
9
10
11
12
VCCA
VCC
PLL_SEL
VEE
nQ4
Q5
nQ5
Feedback
Divider
VCC
ICS84324
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
F_SEL1
MR
PLL_SEL
F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
1
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
VCC
Type
Description
Output
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Core supply pins.
3, 4
5, 6
7, 8
9, 10
11, 12
13, 16, 24
14, 18
VEE
PLL_SEL
VCCA
Negative supply pins.
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2.
LVCMOS / LVTTL interface levels.
15
Input
Pullup
17
Power
Analog supply pin.
19, 20
XTAL2, XTAL1 Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
21
MR
Input Pulldown
22
23
F_SEL1
F_SEL0
Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Input Pullup Output frequency select pin. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
2
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VCC + 0.5 V
-0.5V to VCC + 0.5V
Outputs, VCC
Package Thermal Impedance, θJA 50°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
135
20
mA
mA
ICCA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PLL_SEL, MR,
F_SEL0, F_SEL1
PLL_SEL, MR,
F_SEL0, F_SEL1
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
MR, F_SEL1
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
IIH
PLL_SEL, F_SEL0
MR, F_SEL1
V
-5
IIL
Input Low Current
PLL_SEL, F_SEL0
VCC = 3.465V, VIN = 0V
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
3
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
FOUT
tjit(cc)
tsk(o)
tR
Output Frequency
53.125
125
MHz
ps
Cycle-to-Cycle Jitter; NOTE 2
Output Skew; NOTE 1, 2
Output Rise Time
25
TBD
ps
20% to 80%
20% to 80%
200
200
650
650
ps
tF
Output Fall Time
ps
odc
tPW
Output Duty Cycle
50
%
Output Pulse Width
PLL Lock Time
tPERIOD/2 - TBD
tPERIOD/2 + TBD
1
ps
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCC/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
4
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TYPICAL PHASE NOISE AT 106.25MHZ
USING A 25MHZ QUARTZ CRYSTAL
0
-10
-20
-30
-40
Process Result
Source
10.000
40.000M
106.250M
Start Freq.
Stop Freq.
Freq. carrier
Hz
Hz
-50
-60
Hz
-70
-80
-90
Mode
Integral
Noise only
sec. rms
4.15p
Execute
Plot
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1
100
1k
10k
100k
1M
10M
100M
637KHz to 10MHz, 4.15ps RMS
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
5
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PARAMETER
MEASUREMENT
I
NFORMATION
VCC, VCCA = 2V
SCOPE
Qx
nQx
Qx
LVPECL
nQy
Qy
nQx
tsk(o)
VEE = -1.3V ± 0.165
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQ0:nQ5
Q0:Q5
80%
80%
20%
20%
➤
➤
t
cycle n
➤
tcycle n+1
➤
Clock Outputs
t
t
F
R
t
jit(cc) = tcycle n –tcycle n+1
1000 Cycles
O
UTPUT
RISE/FALL
T
IME
C
YCLE
-
TO-CYCLE
J
ITTER
nQ0:nQ5
Q0:Q5
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
odc & tPERIOD
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
6
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84324 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS84324 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3.
19
XTAL2
C1
18pF
25MHz X1
20
XTAL1
C2
22pF
ICS84324
Figure 3. CRYSTAL INPUt INTERFACE
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
7
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs. The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
8
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84324.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84324 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 468mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 468mW + 181mW = 649mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.649W * 43°C/W = 98°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA FOR 24-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
9
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω) * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
10
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84324 is: 2882
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
11
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
12
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS84324DM
Marking
Package
24 Lead SOIC
Count
30 per tube
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS84324DM
ICS84324DM
ICS84324DMT
24 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84324DM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 30, 2003
13
相关型号：
ICS84324EMLF
Clock Generator, 125MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24
IDT
ICS84324EMLFT
Clock Generator, 125MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24
IDT
ICS84324EMT
Clock Generator, 125MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24
IDT
©2020 ICPDF网 联系我们和版权申明