ICS8516EYLF-T [IDT]
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48;
| 型号： | ICS8516EYLF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件： | 总11页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
GENERAL DESCRIPTION
FEATURES
The ICS8516 is a low skew, high performance • 16 Differential 3.3V LVDS outputs
,&6
1-to-16 Differential-to-3.3V LVDS Clock Distribu-
• Differential CLK, nCLK pair
HiPerClockS™
tion Chip and a member of the HiPerClockS™ fam-
ily of High Performance Clock Solutions from ICS.
ICS8516 CLK, nCLK pair can accept any differ-
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
ential input levels and translates them to 3.3V LVDS output
levels. Utilizing Low Voltage Differential Signaling (LVDS) the
ICS8516 provides a low power, low noise, point-to-point solu-
tion for distributing clock signals over controlled impedances
of 100Ω.
• Maximum output frequency up to 400MHz
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with
resistor bias on nCLK input
Dual output enable inputs allow the ICS8516 to be used in a
1-to-16 or 1-to-8 input/output mode.
• Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well de-
fined performance and repeatability.
• Designed to meet or exceed the requirements of
ANSI TIA/EIA-644
• Output skew: 200ps (maximum)
• Part-to-part skew: TBD
• Propagation delay: 2.9ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
48 47 46 45 44 43 42 41 40 39 38 37
VDD
nQ5
Q5
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
Q0
Q15
2
nQ10
Q10
nQ11
Q11
VDD
nQ0
nQ15
3
Q1
nQ1
Q14
nQ14
nQ4
Q4
4
5
Q2
nQ2
Q13
nQ13
VDD
GND
nQ3
Q3
6
ICS8516
7
GND
nQ12
Q12
nQ13
Q13
VDD
8
Q12
nQ12
Q3
nQ3
9
nQ2
Q2
10
11
12
Q4
nQ4
Q11
nQ11
VDD
13 14 15 16 17 18 19 20 21 22 23 24
Q10
nQ10
Q5
nQ5
Q9
nQ9
Q6
nQ6
Q8
nQ8
Q7
nQ7
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
OE1
OE2
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8516EY
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REV. C OCTOBER 8, 2001
1
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 7, 12,
25, 31, 36
VDD
Power
Positive supply pins. Connect to 3.3V.
2, 3
4, 5
nQ5, Q5
nQ4, Q4
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 17, 20,
30, 41, 44
GND
Power
Power supply ground. Connect to ground.
8, 9
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
Output
Output
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
10, 11
13, 14
15, 16
18
Pullup
Inverting differential clock input.
19
CLK
Input
Pulldown Non-inverting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
21, 22
23, 24
26, 27
28, 29
32, 33
34, 35
37, 38
39, 40
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Q11, nQ11
Q10, nQ10
Q9, nQ9
Q8, nQ8
Output
Output
Output
Output
Output
Output
Output
Output
Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15;
OE1 controls outputs Q0, nQ0 thru Q7, nQ7.
42, 43
OE2, OE1
Input
Pullup
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8516EY
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REV. C OCTOBER 8, 2001
2
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
KΩ
KΩ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
OE1
OE2
Q0 thru Q7
Hi Z
nQ0 thru nQ7
Q8 thru Q15
nQ8 thru nQ15
Hi Z
0
1
0
1
0
0
1
1
Hi Z
ACTIVE
Hi Z
Hi Z
Hi Z
ACTIVE
Hi Z
Hi Z
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0 thru Q15
nQ0 thru nQ15
HIGH
0
1
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
LOW
0
Biased; NOTE 1
HIGH
1
Biased; NOTE 1
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section on page 9, Figure 8, which discusses wiring the differential
input to accept single ended levels.
8516EY
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REV. C OCTOBER 8, 2001
3
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VDDI
Outputs, VDDO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
Positive Supply Voltage
Power Supply Current
3.135
3.465
V
IDD
140
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage OE1, OE2
2
VDD + 0.3
V
V
Input Low Voltage OE1, OE2
Input High Current OE1, OE2
Input Low Current OE1, OE2
-0.3
0.8
5
VDD = VIN = 3.465V
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
NOTE: Outputs terminated with 50Ω to VDD/2. See page 6, Figure 1, 3.3V Output Load Test Circuit.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK
V
IN = VDD = 3.465V
VIN = VDD = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
Input High Current
IIH
nCLK
CLK
V
-5
IIL
Input Low Current
Differential Input
nCLK
VDD = 3.465V, VIN = 0V
-150
VTH
VTL
100
mV
mV
High Threshold Voltage
Differential Input
-100
Low Threshold Voltage
VPP
Peak-to-Peak Voltage
0.15
0.5
1.3
V
V
VCMR
Common Mode Voltage Range
VDD - 0.85
8516EY
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REV. C OCTOBER 8, 2001
4
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
VOD
∆ VOD
VOS
∆ VOS
IOZ
Differential Output Voltage
350
mV
mV
V
VOD Magnitude Change
Offset Voltage
1.25
5
VOS Magnitude Change
High Impedance Leakage Current
Power Off Leakage
mV
µA
µA
mA
mA
V
1
IOFF
1
IOSD
IOS
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
-3.5
-3.5
1.34
1.06
VOH
VOL
Output Voltage Low
V
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
fMAX Output Frequency
tPD
Minimum
Typical
Maximum Units
400
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 900MHz
2.4
tsk(o)
tsk(pp)
tR
150
ps
TBD
ps
30ꢀ TO 70ꢀ at 50MHz
30ꢀ TO 70ꢀ at 50MHz
500
500
50
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8516EY
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REV. C OCTOBER 8, 2001
5
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
PARAMETER MEASUREMENT INFORMATION
3.3V
SCOPE
Qx
LVDS
3.3V 5ꢀ POWER SUPPLY
Float GND
+
-
nQx
FIGURE 1 - 3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nCLK
CLK
VPP
VCMR
Cross Points
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
8516EY
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REV. C OCTOBER 8, 2001
6
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
nQx
Qx
nQy
Qy
tsk(o)
FIGURE 3 - OUTPUT SKEW
nQx
PART 1
Qx
nQy
PART 2
Qy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
70ꢀ
70ꢀ
VSWING
30ꢀ
30ꢀ
Clock Inputs
and Outputs
trise
tfall
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
8516EY
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REV. C OCTOBER 8, 2001
7
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
nCLK
CLK
nQ0 - nQ15
Q0 - Q15
tPD
FIGURE 6 - PROPAGATION DELAY
nCLK, nQ0 - nQ15
CLK, Q0 - Q15
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
8516EY
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REV. C OCTOBER 8, 2001
8
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8516EY
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REV. C OCTOBER 8, 2001
9
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
PACKAGE OUTLINE - Y SUFFIX
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
8516EY
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REV. C OCTOBER 8, 2001
10
PRELIMINARY
ICS8516
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-3.3V LVDS CLOCK DISTRIBUTION CHIP
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8516EY
Marking
Package
48 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8516EY
ICS8516EY
ICS8516EY-T
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8516EY
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REV. C OCTOBER 8, 2001
11
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