ICS85214AGT [IDT]
Low Skew Clock Driver, 85214 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS85214AGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 85214 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-
HSTL FANOUT BUFFER
ICS85214
Description
Features
The ICS85214 is a low skew, high performance
• Five differential HSTL compatible outputs
S
IC
1-to-5 Differential-to-HSTL Fanout Buffer and a
member of the HiPerClockS™family of High
Performance Clock Solutions from IDT. The CLK0,
CLK0 pair can accept most standard differential
• Selectable differential CLK0, CLK0 or LVCMOS/LVTTL clock
HiPerClockS™
inputs
• CLK0, CLK0 pair can accept the following differential input
levels: LVPECL, LVDS, HSTL, HCSL, SSTL
input levels. The single ended CLK1 input accepts LVCMOS or
LVTTL input levels. Guaranteed output and part-to-part skew
characteristics make the ICS85214 ideal for those clock
distribution applications demanding well defined performance and
repeatability.
• CLK1 can accept the following input levels: LVCMOS or LVTTL
• Output frequency up to: 700MHz
• Translates any single-ended input signal to HSTL levels with
resistor bias on CLK0 input
• Output skew: 30ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 85°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Pulldown
CLK_EN
D
Q0
Q0
Q1
Q1
Q2
Q2
Q3
1
2
20
19
VDDO
CLK_EN
Q
LE
Pullup
CLK0
CLK0
3
4
18
17
VDD
nc
Pulldown
0
Q0
Q0
5
6
7
8
9
16 CLK1
Pulldown
Pulldown
CLK1
1
15
14
13
CLK0
CLK0
nc
Q1
Q1
CLK_SEL
Q3
Q4
Q4 10
Q2
Q2
12 CLK_SEL
GND
11
Q3
Q3
ICS85214
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
IDT™ / ICS™ HSTL FANOUT BUFFER
1
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, Q0
Q1, Q1
Q2, Q2
Q3, Q3
Q4, Q4
GND
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Power supply ground.
3, 4
5, 6
7, 8
9, 10
11
Clock select input. When HIGH, selects differential CLK1input. When LOW,
selects CLK0, CLK0 inputs. LVCMOS/LVTTL interface levels.
12
CLK_SEL
Input
Pulldown
13, 17
14
nc
Unused
Input
No connect.
CLK0
CLK0
Pullup
Inverting differential clock input.
15
Input
Pulldown Non-inverting differential LVPECL clock input.
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Positive supply pin.
16
18
CLK1
VDD
Input
Power
Synchronizing clock enable. When LOW, clock outputs follow clock input.
Pulldown When HIGH, Qx outputs are forced low, Qx outputs are forced high.
LVTTL/LVCMOS interface levels.
19
20
CLK_EN
Input
VDDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to intenal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
IDT™ / ICS™ HSTL FANOUT BUFFER
2
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
CLK_EN
Q0:Q4
Enabled
Q0:Q4
Enabled
0
1
Disabled; LOW
Disabled; HIGH
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 , CLK0 inputs as described in Table 3B.
Enabled
Disabled
CLK0
CLK0
CLK_EN
Q0:Q4
Q0:Q4
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK0 or CLK1
CLK0
Q[0:4]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Q[0:4]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
0
0
1
1
0
Baised; NOTE 1
1
Baised; NOTE 1
Baised; NOTE 1
Baised; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
IDT™ / ICS™ HSTL FANOUT BUFFER
3
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
Outputs, VDDO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.0
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
1.6
1.8
V
80
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 850°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
0.8
Units
VIH
VIL
Input High Voltage
2
V
V
Input Low Voltage
Input High Current
-0.3
CLK1,
CLK_EN, CLK_SEL
IIH
IIL
VDD = VIN = 3.465V
150
µA
µA
CLK1,
CLK_EN, CLK_SEL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK
CLK
CLK
CLK
VDD = VIN = 3.465V
5
IIH
Input High Current
VDD = VIN = 3.465V
150
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD – 0.85
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single-ended applications, the maximum input voltage for CLK, CLK is VDD + 0.3V.
IDT™ / ICS™ HSTL FANOUT BUFFER
4
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Table 4D. HSTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Current;
NOTE 1
VOH
1.0
1.4
V
Output Low Current;
NOTE 1
VOL
0
0.4
60% x (VOH – VOL) + VOL
1.1
V
V
V
Output
Crossover Voltage
VOX
38% x (VOH – VOL) + VOL
0.6
Peak-toPeak
Output Voltage Swing
VSWING
NOTE 1: Outputs termination with 50Ω to ground.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum
Units
MHz
MHz
ns
CLK0, CLK0
CLK1
700
300
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
IJ 700MHz
1.0
1.8
30
tsk(o)
tsk(pp)
tR / tF
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
ps
250
700
54
ps
20% to 80%
200
46
ps
CLK0, CLK0
Output Duty Cycle
CLK1
%
odc
45
55
%
All parameters measured at fMAX unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from either the differential input crossing point or VDD/2 to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.Parameter Measurement Information
IDT™ / ICS™ HSTL FANOUT BUFFER
5
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Parameter Measurement Information
3.3V 5%
1.8V 0.2V
V
DD
,
,
SCOPE
,
Qx
V
DD
CLK0
CLK0
V
DDO
VPP
VCMR
Cross Points
HSTL
nQx
GND
GND
GND = 0V
3.3V/1.8V Output Load AC Test Circuit
Differential Input Level
Part 1
Qx
Qx
Qx
Qx
Part 1
Qy
Qy
Qy
Qy
tsk(o)
tsk(pp)
Output Skew
Part-to-Part Skew
CLK0
CLK0
CLK1
Q0:Q4
Q0:Q4
Q0:Q4
Q0:Q4
tPD
tPD
Differential Propagation Delay
LVCMOS Propagation Delay
IDT™ / ICS™ HSTL FANOUT BUFFER
6
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Parameter Measurement Information, continued
Q0:Q4
Q0:Q4
80%
tF
tPW
80%
tR
tPERIOD
VSWING
20%
Clock
Outputs
20%
tPW
odc =
x 100%
tPERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ HSTL FANOUT BUFFER
7
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Differential Clock Input Interface
The CLK0 /CLK0 accepts LVDS, LVPECL, HSTL, SSTL, HCSL and
other differential signals. The signals must meet the VPP and VCMR
input requirements. Figures 3A to 3D show interface examples for
the HiPerClockS CLK0/CLK0 input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example, in Figure
3A, the input termination applies for IDT HiPerClockS HSTL
drivers. If you are using an HSTL driver from another vendor, use
their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
HiPerClockS
Input
nCLK
LVPECL
HiPerClockS
LVHSTL
R1
50
R2
50
Input
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 3A. HiPerClockS CLK/CLK Input Driven by an
IDT HiPerClockSHSTLDriver
Figure 3B. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
HiPerClockS
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 3C. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVDS Driver
IDT™ / ICS™ HSTL FANOUT BUFFER
8
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins:
HSTL Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused HSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
CL0K/CLK0 INPUT:
For applications not requiring the use of the differential input, both
CLK0 and CLK0 can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK0 to
ground.
CLK1 INPUT:
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK1 input to ground.
Schematic Example
Figure 4 shows a schematic example of the ICS85214. In this
example, the input is driven by an IDT HiPerClockS HSTL driver.
The decoupling capacitors should be physically located near the
power pin. For ICS85214, the unused clock outputs can be left
floating.
Zo = 50
+
Zo = 50
-
R2
50
R1
50
U1
1.8V
R12 1K
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
GND
nQ4
Q4
Zo = 50
Zo = 50
CLK_SEL
nc
nQ3
Q3
+
-
Zo = 50 Ohm
Zo = 50 Ohm
nCLK
CLK
nQ2
Q2
SCLK
nc
nQ1
Q1
3.3V
VDD
C2
0.1u
nCLK_EN
VDDO
nQ0
Q0
1.8V
R4
50
R3
50
LVHSTL Driver
R9
50
R10
50
C1
0.1u
ICS85214
Zo = 50
+
-
R11
1K
Zo = 50
R8
50
R7
50
Figure 4. ICS85214 HSTL Buffer Schematic Example
IDT™ / ICS™ HSTL FANOUT BUFFER
9
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85214.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85214 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 850mA = 227.2mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 x 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 227.2mW + 144mW = 391.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.391W * 66.6°C/W = 111°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
IDT™ / ICS™ HSTL FANOUT BUFFER
10
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 6.
VDDO
Q1
VOUT
RL
50Ω
Figure 6. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX
)
Pd_L = (VOL_MAX/RL) * (VDDO_MAX- VOL_MAX
)
Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
IDT™ / ICS™ HSTL FANOUT BUFFER
11
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Transistor Count
The transistor count for ICS85214 is: 674
Package Outline and Package Dimension
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
2
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
f
&
d
IDT™ / ICS™ HSTL FANOUT BUFFER
12
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
85214AG
85214AGT
85214AGLF
85214AGLFT
Marking
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 85°C
0°C to 85°C
0°C to 85°C
0°C to 85°C
ICS85214AG
ICS85214AG
ICS85214AGLF
ICS85214AGLF
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ HSTL FANOUT BUFFER
13
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
Changed LVHSTL to HSTL throughout the datasheet.
A
7/17/03
T2
2
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical
1
9
Features Section - added Lead-Free Bullet.
Added Recommendation of Unused Input and Output Pins.
Ordering Information Table - added Lead-Free part number, marking, and note.
Changed format throughout the datasheet.
A
3/13/07
T9
13
IDT™ / ICS™ HSTL FANOUT BUFFER
14
ICS85214AG REV. A MARCH 13, 2007
ICS85214
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
+408 284 8200 (outside U.S.)
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
www.IDT.com
相关型号：
ICS85214AGT-LF
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS8521AY
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
IDT
ICS8521AYI-03LF
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
ICS8521AYI-03LFT
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
IDT
ICS8521AYLF
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
IDT
ICS8521AYYT
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
IDT
©2020 ICPDF网 联系我们和版权申明