ICS8523AGLF [IDT]
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, MO-153, TSSOP-20;
| 型号： | ICS8523AGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, MO-153, TSSOP-20 光电二极管 |
| 文件： | 总7页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8523 is a low skew, high performance, • 4 LVHSTL outputs each with the ability to drive 50Ω to ground
,&6
1-to-4 LVHSTL clock fanout buffer and a member
• Selectable differential HSTL or PECL clock inputs
of the HiPerClockS™ family of High Performance
HiPerClockS™
Clock Solutions from ICS. The ICS8523 has
selectable clock inputs that accept either HSTL
or PECL input levels. The clock enable is synchronous which
eliminates the runt clock pulses which occur during asynchro-
nous enabling and disabling of the outputs.
• Voh (max) = 1.2V
• Input crossover voltage, Vx, 0.68V ≤ Vx ≤ 0.9V
• Output frequency up to 500MHz
• 30ps output skew
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
• 3.3V input, 1.8V output operating supply voltages
• LVCMOS / LVTTL control inputs
• 20 lead TSSOP
• 0°C to 70°C ambient operating temperature
• Industrial temperature version available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
VEE
CLK_EN
CLK_SEL
HCLK
nHCLK
PCLK
nPCLK
nc
nc
VDDI
nD
LE
CLK_EN
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
Q
HCLK
nHCLK
PCLK
0
1
Q0
nQ0
nPCLK
Q1
nQ1
CLK_SEL
nQ3
Q2
nQ2
ICS8523
Q3
nQ3
20-Lead TSSOP
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
8523
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REV. C FEBRUARY 9, 2001
1
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Input
Negative power supply pin. Connect to power supply ground.
Synchronous clock enable. When HIGH clock outputs follows clock input.
When LOW, Q outputs are force low, nQ outputs are force high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH selects differential HSTL inputs.
When LOW selects differential PECL inputs. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
HCLK
nHCLK
PCLK
Input
Input
Pulldown Non-inverting differential HSTL clock input.
Pullup Inverting differential HSTL clock input.
Pulldown Non-inverting differential PECL clock input.
5
6
Input
7
nPCLK
nc
Input
Pullup
Inverting differential PECL clock input.
Unused pins.
8, 9
10
Unused
Power
Output
Power
Output
VDDI
Input power supply pin. Connect to 3.3V.
Differential clock outputs. LVHSTL interface levels.
Output power supply. Connect to 1.8V.
Differential clock outputs. LVHSTL interface levels.
Differential clock outputs. LVHSTL interface levels.
Differential clock outputs. LVHSTL interface levels.
11, 12
13, 18
14, 15
16, 17
19, 20
nQ3, Q3
VDDO
nQ2, Q2
nQ1, Q1 Output
nQ0, Q0 Output
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
HCLK, nHCLK
PCLK, nPCLK
pF
pF
Input
Capacitance
CIN
CLK_EN,
CLK_SEL
pF
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN Input Pulldown Resistor
8523
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REV. C FEBRUARY 9, 2001
2
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Q0 thru Q3
LOW
nQ0 thru nQ3
HIGH
0
0
1
1
0
1
0
1
LOW
HIGH
Active
Active
Active
Active
In the active mode the state of the output is a function of the HCLK , nHCLK and PCLK, nPCLK inputs as described
in Table 3B.
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
nHCLK or
nPCLK
HCLK or PCLK
Q0 thru Q3
nQ0 thru nQ3
0
0
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Single ended use requires that one of the differential input be biased. The voltage at the biased input sets the
switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a 10KΩ
resistor from the input pin to VDD, 10KΩ resistor from the input pin to ground and a 0.1µF capacitor from the input to
ground. The resulting switch point is VDD/2 ± 300mV.
8523
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REV. C FEBRUARY 9, 2001
3
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
Ambient Operating Temperature
Storage Temperature
-0.5V to VDDI + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 1.8V±10%, TA=0°C TO 70°C
Symbol
VDDI
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Input Power Supply Voltage
Ouptut Power Supply Voltage
Power Supply Current
3.465
2.0
V
V
VDDO
IEE
1.6
1.8
50
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 1.8V±10%, TA=0°C TO 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input High Voltage CLK_EN, CLK_SEL
Input Low Voltage CLK_EN, CLK_SEL
2
3.765
0.8
5
V
VIL
-0.3
V
CLK_EN
Input High Current
CLK_SEL
µA
µA
µA
µA
IIH
IIL
150
CLK_EN
Input Low Current
CLK_SEL
-150
-5
TABLE 4C. LVPECL DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 1.8V±10%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
PCLK
150
5
µA
µA
µA
IIH
IIL
Input High Current
nPCLK
PCLK
-5
Input Low Current
nPCLK
-150
0.1
µA
V
VPP
Peak-to-Peak Input Voltage
1.3
1.3
VCMR
Common Mode Input Voltage; NOTE 1
0.13
V
NOTE 1: Common mode voltage for PECL is defined as the minimum VIH. VCMR is compatible with DCM, LVDS, LVPECL
and SSTL input levels.
8523
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REV. C FEBRUARY 9, 2001
4
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. LVHSTL DC CHARACTERISTICS, VDDI = 3.3V±5%, VDDO = 1.8V±10%, TA=0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
HCLK
150
5
µA
µA
µA
µA
V
IIH
IIL
Input High Current
nHCLK
HCLK
-5
-150
0.1
0.13
1.0
0
Input Low Current
nHCLK
VPP
Peak-to-Peak Input Voltage
1.3
1.3
1.2
0.4
VCMR
VOH
VOL
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
V
V
V
40% x
(VOH-VOL)
+ VOL
60% x
(VOH-VOL)
+ VOL
VOX
Output Crossover Voltage
V
NOTE 1: Common mode voltage for HSTL is defined as the crossover voltage. VCMR is compatible with DCM,
LVDS, LVPECL and SSTL input levels.
NOTE 2: For single ended applications the maximum input voltage for HCLK and nHCLK is VDD + 0.3V.
NOTE 3: Outputs terminated with 50Ω to ground. The power dissipation of a terminated output pair is 32mW.
TABLE 5. ELECTRICAL AC CHARACTERISTICS, VCC=3.3V±5%, VCCO=1.8V±10%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
tpLH
tpHL
tsk(o)
tsk(pp)
tjit(Ø)
tR
Maximum Input Frequency
650
2.0
2.0
30
MHz
ns
Propagation Delay, Low-to-High; NOTE 2
Propagation Delay, High-to-Low; NOTE 2
Output Skew; NOTE 3
1.0
1.0
ns
ps
Part-to-Part; NOTE 4
150
0
ps
Input-to-Output Jitter; NOTE 5
Output Rise Time
ps
30% to 70%
30% to 70%
100
100
800
800
ps
tF
Output Fall Time
ps
tCYCLE/2
-TBD
tCYCLE/2
+TBD
tPW
Output Pulse Width
tCYCLE/2
ns
tS
tH
Clock Enable Setup Time
Clock Enable Hold Time
1.0
1.0
ns
ns
NOTE 1: All parameters measured at 500Mhz unless noted otherwise.
NOTE 2: Measured from the 50% point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the 50% point of the input to the differential output crossing point.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Measured from the 50% point of like inputs to the differential output crossing point.
NOTE 5: Measured by triggering on input signal and measuring the largest displacement between output cycles.
8523
www.icst.com
REV. C FEBRUARY 9, 2001
5
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
c
20
1
11
L
E1
E
10
α
D
A2
A
A1
-c-
e
b
SEATING
PLANE
aaa
c
TABLE 6. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MIN
Inches
MAX
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
--
.047
.006
.041
.012
.008
.260
A1
A2
b
0.05
0.80
0.19
0.09
6.40
.002
.032
.007
c
.0035
.252
D
E
6.40 BASIC
0.65 BASIC
0.252 BASIC
E1
e
4.30
4.50
.169
.177
.0256 BASIC
L
0.45
0°
0.75
8°
.018
0°
.030
8°
a
aaa
--
0.10
--
.004
Reference Document: JEDEC Publication 95, MO-153
8523
www.icst.com
REV. C FEBRUARY 9, 2001
6
PRELIMINARY
ICS8523
LOW SKEW, 1-TO-4
LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8523AG
Marking
Package
Count
75
Temperature
0°C to 70°C
0°C to 70°C
ICS8523AG
ICS8523AG
20 lead TSSOP
ICS8523AGT
20 lead TSSOP on Tape and Reel
2500
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
8523
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REV. C FEBRUARY 9, 2001
7
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