ICS853011BGT [IDT]
Low Skew Clock Driver, 853011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8;
| 型号： | ICS853011BGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 853011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8 光电二极管 |
| 文件： | 总17页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V
LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853011 is a low skew, high perfor- • 2 differential 2.5V/3.3V LVPECL / ECL outputs
ICS
HiPerClockS™
mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
• 1 differential PCLK, nPCLK input pair
ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853011
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853011 ideal for those
clock distribution applications demanding well defined
performance and repeatability.
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Output skew: 5ps (typical)
• Part-to-part skew: 130ps (maximum)
• Propagation delay: 390ps (maximum)
• Additive phase jitter, RMS: 0.06ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both Standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
Vcc
1
2
3
4
8
7
6
5
Q0
nQ0
PCLK
nPCLK
VEE
PCLK
nPCLK
Q1
nQ1
nQ1
ICS853011
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
ICS853011
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
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LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
3, 4
5
Pullup/
Pulldown
6
nPCLK
Input
Clock input. VCC/2 default when left floating. LVPECL interface levels.
7
8
PCLK
VCC
Input
Pulldown Clock input. Default LOW when left floating. LVPECL interface levels.
Positive supply pin.
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
RPULLDOWN
RVCC/2
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Pulldown Resistor
Pullup/Pulldown Resistors
75
50
kΩ
kΩ
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
Package Thermal Impedance, θJA 101.7°C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
25
V
mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
2.175 2.275 2.38 2.225 2.295 2.37
1.405 1.545 1.68 1.425
Typ
Max
Min
Typ
Max
Min
Max
2.22
2.295 2.365
1.535 1.63
V
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
1.52 1.615 1.44
150
1.2
800
1200
3.3
150
1.2
800
1200
3.3
150
1.2
800
1200
3.3
Input High Voltage
Common Mode Range; NOTE 2, 3
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
-10
-10
µA
µA
PCLK
-10
Input
Low Current
IIL
-150
-150
nPCLK
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 2.5V;VEE = 0V
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
1.375 1.475 1.58
0.605 0.745 0.88
1.425 1.495 1.57
1.42 1.495 1.565
V
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
0.625 0.72 0.815 0.64 0.735 0.83
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
150
1.2
800
1200
2.5
150
1.2
800
1200
2.5
150
1.2
800
1200
2.5
Input High Voltage
Common Mode Range; NOTE 2, 3
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
-10
-10
-10
µA
µA
PCLK
Input
Low Current
IIL
-150
-150
-150
nPCLK
For notes see above Table 3B, 3.3V LVPECL DC Characteristics.
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
-40°C
25°C
85°C
Symbol Parameter
Units
Min
-1.125
-1.895
150
Typ Max
Min
-1.075
-1.875
150
Typ Max
Min
-1.08
-1.86
150
Typ Max
-1.025
-1.755
800
-0.92
-1.62
1200
-1.005
-1.78
800
-0.93
-1.685
1200
-1.005 -0.935
V
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
-1.765
800
-1.67
1200
Input High Voltage
Common Mode Range; NOTE 2, 3
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
-10
-10
-10
µA
µA
Input
PCLK
IIL
-150
-150
-150
Low Current nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
-40°C
Min Typ
25°C
Max Min Typ
85°C
Symbol Parameter
Units
Max Min Typ
Max
>3
fMAX
Output Frequency
>3
375
20
>3
390
20
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
245
260
275
415
20
tsk(o)
tsk(pp)
5
5
5
ps
Part-to-Part Skew; NOTE 3, 4
130
130
150
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section,
Integration Range: 12KHz to 20MHz
tjit
0.06
0.06
0.06
ps
tR/tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
70
48
250
52
80
48
250
52
100
48
250
52
ps
%
f ≤ 1GHz
50
50
50
All parameters are measured at f ≤ 1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
Additive Phase Jitter
155.52MHz@12kHz to 20MHz
= 0.06ps (typical)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
,
Qx
VCCO
nPCLK
LVPECL
VEE
VPP
VCMR
Cross Points
PCLK
VEE
nQx
-1.8V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
PCLK
80%
tF
80%
VSWING
20%
nQ0, nQ1
Clock
20%
Outputs
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 2A to 2E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
R1
120
R2
120
PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTTERMINATION
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 4C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853011.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 25mA = 95mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 95mW + 61.88mW = 156.88mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W
per Table 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.157W * 103.3°C/W = 101.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PINTSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
–0.935V
CC_MAX
OH_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
= 1.67V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
12
ICS853011
TSD
LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6A. θJAVS. AIR FLOWTABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 6B. θJAVS. AIR FLOWT ABLE FOR 8 LEAD TSSOP
θ
JA by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS853011 is: 96
Pin compatible with MC100LVEP11 and SY100EP11U
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
13
ICS853011
TSD
LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 8 LEADTSSOP
TABLE 7A. PACKAGE DIMENSIONS
TABLE 7B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUN
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.10
0.15
0.97
0.38
0.23
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
1.27 BASIC
E1
e
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e1
L
L
0.40
0°
0.80
8°
α
α
Reference Document: JEDEC Publication 95, MS-012
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
14
ICS853011
TSD
LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
8 lead SOIC
Shipping Packaging
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853011BM
ICS853011BMT
ICS853011BMLF
ICS853011BMLFT
ICS853011BG
853011BM
853011BM
tube
2500
tube
2500
tube
2500
tube
2500
8 lead SOIC
853011BL
853011BL
011B
8 lead "Lead Free" SOIC
8 lead "Lead Free" SOIC
8 lead TSSOP
ICS853011BGT
ICS853011BGLF
ICS853011BGLFT
011B
8 lead TSSOP
11BL
8 lead "Lead Free" TSSOP
8 lead "Lead Free" TSSOP
11BL
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
15
ICS853011
TSD
LOW SKEW, 1-TO-2DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T3B
3
3.3V LVPECL Table - changed VOH @ 85° , from 2.295V min. to 2.22V min.
and 2.33V typical to 2.295V typical.
T3C
T3D
4
4
2.5V LVPECL Table - changed VOH @ 85°, from 1.495V min. to 1.42V min. and
1.53V typical to 1.495V typical.
B
9/2/03
ECL Table - changed VOH @ 85°, from -1.005V min. to -1.08V min. and --
0.97V typical to -1.005V typical.
6
8
8
Updated LVPECL Output Termination Diagrams.
Updated LVPECL Clock Input Inteface Figure 4D.
Corrected Figure 4C.
B
C
11/12/03
9/7/04
Added "Lead Free" Part/Order Number rows.
AC Characteristics Table - added Additive Phase Jitter.
Added Additive Phase Jitter Section.
13
4
5
T4
T8
1
Features Section - added Lead-Free bullet.
10
15
Added "Recommendations for Unused Input and Output Pins".
C
C
7/13/05
11/2/05
Ordering Information Table - corrected Lead-Free marking and added Lead-
Free note.
Pin Assignment - added 8 Lead TSSOP package.
Absolute Maximum Ratings - added TSSOP to Package Thermal Impedance.
Power Considerations - added 8 Lead TSSOP Thermal Resistance.
Added 8 Lead TSSOP Reliability Information.
1
3
11
13
14
15
T5B
T6B
Added TSSOP Package Outline and Dimensions.
Ordering Information - Added 8 Lead TSSOP part number and marking.
T8
IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
16
85301
LO22.5V/3.3VLVPECL/ECLFANOUT BUFFER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
clockhelp@idt.com
408-284-8200
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
+408 284 8200 (outside U.S.)
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
XX-XXXX-XXXXX
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