ICS8535AG-11LF [IDT]
Low Skew Clock Driver, 4 True Output(s), 4 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS8535AG-11LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 4 True Output(s), 4 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总14页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8535-11 is a low skew, high performance • 4 differential 3.3V LVPECL outputs
ICS
1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
LVPECL fanout buffer and a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS.The ICS8535-11 has select-
• Selectable LVCMOS/LVTTL CLK or crystal inputs
HiPerClockS™
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 266MHz
• Output skew: 35ps (maximum)
able single ended clock or crystal inputs. The single ended
clock input accepts LVCMOS or LVTTL input levels and
translate them to 3.3V LVPECL levels. The output enable is
internally synchronized to eliminate runt pulses on the out-
puts during asynchronous assertion/deassertion of the clock
enable pin.
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
Guaranteed output and part-to-part skew characteristics
make the ICS8535-11 ideal for those applications demand-
ing well defined performance and repeatability.
• 0°C to 70°C ambient operating temperature
• IndustrialTemperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VEE
CLK_EN
CLK_SEL
CLK
Q0
D
CLK_EN
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
Q
LE
CLK
0
1
Q0
nQ0
nc
XTAL1
XTAL2
XTAL1
XTAL2
nc
nc
VCC
Q1
nQ1
9
10
CLK_SEL
nQ3
Q2
nQ2
ICS8535-11
20-LeadTSSOP
Q3
nQ3
6.5mm x 4.4mm x 0.92mm package body
G Package
TopView
8535AG-11
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REV. D OCTOBER 20, 2003
1
ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Negative supply pin.
1
VEE
Power
Input
Synchronizing clock enable. When HIGH, clock outputs follows clock
input. When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects XTAL inputs.
When LOW, selects CLK input. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
CLK
nc
Input
Unused
Input
Pulldown Clock input. LVCMOS / LVTTL interface levels.
No connect.
5, 8, 9
6, 7
XTAL1, XTAL2
VCC
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Positive supply pins.
10, 13, 18
11, 12
14, 15
16, 17
19, 20
Power
Output
Output
Output
Output
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
8535AG-11
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2
ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
0
0
1
1
0
1
0
1
Disabled; HIGH
Disabled; HIGH
Enabled
XTAL1, XTAL2
CLK
XTAL1, XTAL2
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling
input clock or crystal oscillator edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK input as described in Table 3B.
Enabled
Disabled
CLK
CLK_EN
nQ0:nQ3
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
nQ0:nQ3
CLK
Q0:Q3
LOW
0
1
HIGH
LOW
HIGH
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
IEE
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VCC + 0.3V
0.8
V
V
-0.3
CLK,
CLK_SEL
VIN = VCC = 3.465V
150
5
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
CLK_EN
V
IN = VCC = 3.465V
VIN = 0V, VCC = 3.465V
IN = 0V, VCC = 3.465V
CLK,
CLK_SEL
-5
IIL
CLK_EN
V
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.4
VCC - 2.0
0.6
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
14
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 6. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
25
Maximum
266
Units
MHz
ns
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
Crystal Oscillator Tollerance
IJ 266MHz
1.0
2.4
tsk(o)
tsk(pp)
tR / tF
35
ps
250
ps
20ꢀ to 80ꢀ @ 50MHz
300
48
700
ps
odc
50
52
ꢀ
oscTOL
1000
ppm
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Measured using CLK input. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
nQx
Qx
VCC
Qx
LVPECL
nQy
Qy
nQx
VEE
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VCC
80ꢀ
tF
80ꢀ
2
CLK
VSWING
20ꢀ
Clock
20ꢀ
nQ0:nQ3
Q0:Q3
Outputs
tR
tPD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
nQ0:nQ3
Q0:Q3
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8535-11. In this should be physically located near the power pin. For ICS8535-11,
example, the XTAL input is selected. The decoupling capacitors the unused clock outputs can be left floating.
Zo = 50
+
Zo = 50
-
3.3V
R2
50
R1
50
R12
1K
U1
R3
50
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VEE
Q0
nQ0
VCC
Q1
nQ1
Q2
nQ2
VCC
Q3
CLK_EN
CLK_SEL
CLK
3.3V
3.3V
NC
XTAL1
XTAL2
NC
NC
VCC
R11
1K
X1
3.3V
C1
10
nQ3
0.1u
ICS8535-11
3.3V
Zo = 50
Zo = 50
+
-
C2
0.1u
C3
0.1u
R8
50
R7
50
R9
50
FIGURE 3. ICS8535-11 LVPECL BUFFER SCHEMATIC EXAMPLE
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.25mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8535-11 is: 428
8535AG-11
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REV. D OCTOBER 20, 2003
11
ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
PACKAGE OUTLINE - G SUFFIX
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS8535AG-11
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8535AG-11
ICS8535AG-11
20 lead TSSOP
ICS8535AG-11T
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8535AG-11
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REV. D OCTOBER 20, 2003
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ICS8535-11
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4, CRYSTAL
O
SCILLATOR
/
LVCMOS-TO-3.3V LVPECL FANOUT
BUFFER
REVISION HISTORY SHEET
Rev Table Page Description of Change
Date
B
T6
5
AC Characteristics table -
tR & tF rows - Test Conditions changed from "30ꢀ to 70ꢀ" to "20ꢀ to 80ꢀ @ 50MHz";
values changed from 100 Min. to 300 Min., and 800 Max. to 700 Max.
tpLH & tpHL changed to tPD . Same values.
6/5/01
tDC changed to odc. Same values.
B
3
Revised Figure 1, CLK_EN Timing Diagram.
Revised Figure 1, CLK_EN Timing Diagram.
10/18/01
10/29/01
B
B
3
5
T5
T1
Shortened Crystal Characteristics table.
ESR row, values have changed from 50Ω Min, 80Ω Max. to 70Ω Max.
Pin Description table - updated CLK_SEL description.
1/11/02
B
B
2
4/9/02
8
6
Added Termination for LVEPCL Outputs section.
5/29/02
Output Load Test Circuit - corrected VEE equation to read
"VEE = -0.5V 0.165V" from "VEE = -0.5V 0.135V".
B
10/4/02
T1
T4B
T4C
T6
2
4
4
5
8
Pin Descriptions table - deleted Pulldown/Pullup from XTAL1 and XTAL2.
LVCMOS table - changed VIH from 3.765V Max. to VCC + 0.3V Max.
LVPECL table - changed VSWING from 0.85V Max. to 1.0V Max.
AC table - changed tsk(pp) from 150ps Max. to 250ps. Max.
Added Schematic in the Application Information Section.
C
1/16/03
Updated format.
T2
2
4
5
7
8
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output rating.
Crystal Characteristics - change ESR from 70Ω max. to 50Ω max.
Updated LVPECL Output Termination diagrams.
Updated Schmatic Example
D
10/20/03
8535AG-11
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REV. D OCTOBER 20, 2003
14
相关型号：
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IDT
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IDT
ICS8535AG-21LFT
Low Skew Clock Driver, 8535 Series, 2 True Output(s), 0 Inverted Output(s), PDSO14, 4.40 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-14
IDT
ICS8535AGI-11
Low Skew Clock Driver, 4 True Output(s), 4 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS8535AGI-11LF
Low Skew Clock Driver, 4 True Output(s), 4 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
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