ICS8602Y [IDT]

Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32;


型号：	ICS8602Y
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32
文件：	总7页 (文件大小：94K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

GENERAL DESCRIPTION

FEATURES

The ICS8602 is a high performance LVCMOS

• Fully integrated PLL

,&6

zero delay buffer and a member of the

• 9 LVCMOS outputs

HiPerClockS™

HiPerClockS™ family of High Performance

Clocks Solutions from ICS. The VCO operates

at a frequency range of 200MHz to 450MHz.

• 15.625MHz to 225MHz output frequency range

• Spread Smart™ for regenerating spread spectrum clocks

Utilizing one of the outputs as feedback to the PLL output

frequencies up to 225MHz can be regenerated with zero

delay with respect to the input. The low impedance

LVCMOS outputs are designed to drive 50Ω series or

parallel terminated transmission lines. The effective fan-

out can be doubled by utilizing the ability of the outputs to

drive two series terminated lines. The differential reference

clock input will accept any differential signal levels.

• Differential reference clock input accepts any differential

signal levels

• 15.625MHz to 225MHz input frequency range

• LVCMOS / LVTTL control inputs

• 3.3V supply voltage

• 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm

package body, 0.8mm package lead pitch

• 0°C to 70°C ambient operating temperature

• Industrial temperature version available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

DIV_SEL0

DIV_SEL1

32 31 30 29 28 27 26 25

VDDA

VDDI

VDDO

÷2

÷4

÷8

÷16

REF_CLK

nREF_CLK

GND

REF_CLK

ICS8602

nREF_CLK

PLL

VDDO

DIV_SEL0

DIV_SEL1

GND

MR / nOE

GND

FB_IN

10 11 12 13 14 15 16

PLL_SEL

MR / nOE

32-Lead LQFP

Y Package

Top View

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

TABLE 1. PIN DESCRIPTIONS

Number

Name

VDDA

Type

Description

Power

Input

PLL power supply pin. Connect to 3.3V.

VDDI

Input and core power supply pin. Connect to 3.3V.

REF_CLK

nREF_CLK

Pulldown Non-inverting differential clock input.

Input

Pullup

Inverting differential clock input.

5, 8, 12

16, 18,

GND

Power

Ground pins. Connect to ground.

22, 25, 29

DIV_SEL0,

DIV_SEL1

Determines output divider valued in Table 3.

LVCMOS / LVTTL interface levels.

Feedback input to phase detector for regenerating clocks with "zero delay"

LVCMOS / LVTTL interface levels.

6, 7

Input

Pulldown

FB_IN

VDDO

10, 14, 20,

24, 27, 31

11,

Power

Output power supply pins. Connect to 3.3V.

Q0,

13, 15,

19, 21,

23, 26,

28, 30

Q1, Q2,

Q3, Q4,

Q5, Q6,

Q7, Q8

Output

Clock outputs. 7Ω typical output impedance. LVCMOS interface levels.

Resets dividers and determine state of the outputs.

LVCMOS / LVTTL interface levels.

Selects between the PLL and the reference clock as the input to the

dividers. When HIGH select PLL. When LOW selects reference clock.

LVCMOS / LVTTL interface levels.

MR/nOE

Input

Pulldown

Pullup

PLL_SEL

TABLE 2. PIN CHARACTERISTICS

Symbol

Parameter

Test Conditions

Minimum Typical Maximum Units

REF_CLK,

nREF_CLK

DIV_SEL0,

DIV_SEL1,

PLL_SEL,

MR/nOE

TBD

CIN

Input Capacitance

Input

Pullup Resistor

Input

RPULLUP

KΩ

RPULLDOWN

KΩ

Pulldown Resistor

VDDA, VDDI, VDDO = 3.47V

TBD

Power Dissipation

Capacitance

(per output)

CPD

VDDA, VDDI = 3.47V,

VDDO = 2.63V

Output

Impedance

ROUT

Ω

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

TABLE 3. CONTROL INPUTS FUNCTION TABLE

FREQUENCY (MHz)

DIV_SEL1

DIV_SEL0

MIN

125

MAX

225

62.5

125

31.25

15.625

62.5

31.25

TABLE 4. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V±5%, TA=0°C TO 70°C

Symbol

fREF

Parameter

Test Conditions

Minimum Typical Maximum Units

Input Reference Frequency

Input Rise Time

225

TBD

MHz

Measured at 20% to 80% points

Measured at 20% to 80% point

Input Fall Time

tDC

Input Reference Duty Cycle

TBD

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

Inputs

Outputs

4.6V

-0.5V to VDD+0.5 V

-0.5V to VDD+0.5V

Ambient Operating Temperature 0°C to 70°C

Storage Temperature -65°C to 150°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Character-

istics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product

reliability.

TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

VDDI

VDDA

VDDO

IDD

Input Power Supply Voltage

3.135

3.3

3.465

Analog Power Supply Voltage

Output Power Supply Voltage

Input Power Supply Current

TABLE 5B. DIFFERENTIAL DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C

Symbol Parameter

Test Conditions

VIN = 3.465V

VIN = 0V

Minimum

Typical

Maximum Units

REF_CLK

nREF_CLK

REF_CLK

nREF_CLK

150

µA

IIH

IIL

Input High Current

-1

Input Low Current

VIN = 0V

-150

VPP

Peak-to-Peak Input Voltage

Common Mode Input Voltage

f = 225MHz

VCMR

TABLE 5C. LVCMOS / LVTTL DC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

DIV_SEL0, DIV_SEL1,

FB_IN, PLL_SEL

MR/nOE

DIV_SEL0, DIV_SEL1,

FB_IN, PLL_SEL

MR/nOE

VIH

VIL

Input High Voltage

3.765

0.8

Input Low Voltage

Input High Current

-0.3

DIV_SEL0, DIV_SEL1,

FB_IN, MR/nOE

VIN = 3.465V

VIN = 0V

150

µA

IIH

IIL

PLL_SEL

DIV_SEL0, DIV_SEL1,

FB_IN, MR/nOE

-5

Input Low Current

PLL_SEL

VIN = 0V

-150

2.6

VDDO = 3.135V

IOH = -36mA

VDDO -3.135V

IOL = 36mA

VOH

VOL

Output High Voltage

Output Low Voltage

0.5

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

TABLE 6. AC CHARACTERISTICS, VDDI=VDDA=VDDO=3.3V±5%, TA=0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

fMAX

tpLH

Maximum Output Frequency

225

MHz

Propagation Delay,

Low-to-High

Propagation Delay,

High-to-Low

PLL_SEL=0V, 0MHz ≤ f ≤ 225MHz

TBD

-170

-220

TBD

tpHL

TBD

+120

+115

125

PLL_SEL = 3.3V, fREF = 133MHz,

fVCO = 133MHz

PLL_SEL = 3.3V, fREF = 50MHz,

fVCO = 50MHz

REF_CLK

nREF_CLK

TBD

PLL Reference

Zero Delay;

NOTE 2

t(Ø)

Measured on rising edge at

VDDO/2

Measured on rising edge at

VDDO/2

tsk(o)

tjit(cc)

Output Skew; NOTE 3

Cycle-to-Cycle Jitter

PLL Lock Time

Output Rise Time

Output Fall Time

TBD

tCYCLE/2

-TBD

tCYCLE/2

+TBD

0MHz ≤ f ≤ 225MHz

tCYCLE/2

2.08

tPW

Output Pulse Width

f = 225MHz

TBD

tEN

Output Enable Time

Output Disable Time

tDIS

NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.

NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.

NOTE 4: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of

adjacent pairs of cycles.

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

PACKAGE OUTLINE - Y SUFFIX

SEATING

PLANE

-C-

ccc

TABLE 7. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBA

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

1.60

0.15

1.45

0.45

0.20

0.05

1.35

0.30

0.09

1.40

0.37

9.00 BASIC

7.00 BASIC

5.60 Ref.

9.00 BASIC

7.00 BASIC

5.60 Ref.

0.80 BASIC

0.60

0.45

0.75

7°

ccc

0.10

Reference Document: JEDEC Publication 95, MS-026

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

PRELIMINARY

ICS8602

Integrated

Circuit

Systems, Incꢀ

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER

TABLE 8. ORDERING INFORMATION

Part/Order Number

ICS8602Y

Marking

ICS8602

Package

32 Lead LQFP

Count

250 per tray

2000

Temperature

0°C to 70°C

ICS8602YT

32 Lead LQFP on Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or

for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for

use in life support devices or critical medical instruments.

8602

www.icst.com/products/hiperclocks.html

REV. C APRIL 5, 2001

ICS8602Y [IDT]

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