ICS86962CYI-01LFT [IDT]
PLL Based Clock Driver, 86962 Series, 17 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS86962CYI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 86962 Series, 17 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总12页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS86962I-01 is a low voltage, low skew
ICS
LVCMOS/LVTTL Zero Delay Buffer and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. With output
frequencies up to 140MHz, the ICS86962I-01 is
• 18 LVCMOS/LVTTL outputs:17 LVCMOS/LVTTL clock outputs,
1 QFB feedback output. 14Ω typical output impedance
HiPerClockS™
• 1 differential LVPECL clock pair
targeted for high performance clock applications. Along with a
fully integrated PLL, the ICS86962I-01 contains frequency
configurable outputs and an external feedback input for regen-
erating clocks with “zero delay”.
• PCLK, nPCLK pair supports the following input types:
LVPECL, LVDS, CML, SSTL
• Input/Output frequency range: 60MHz to 140MHz
• External feedback for “zero delay” clock regeneration
• Output skew: 210ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• Period jitter, RMS: 4ps (maximum)
• Full 3.3V or 2.5V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible to MPC961
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
PCLK
nPCLK
REF
Q1
Q2
24 23 22 21 20 19 18 17
PLL
110MHz - 140MHz
0
1
Q5
Q4
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VDD
Q3
Q4
Q5
Q6
Q7
Q12
Q13
Q14
GND
Q15
Q16
QFB
60MHz - 110MHz
Q3
GND
Q2
ICS86962I-01
FB_IN
FB
Q1
Q0
VDD
F_RANGE
1
2
3
4
5
6
7
8
Q8
Q9
Q10
Q11
Q12
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
TopView
Q13
Q14
Q15
Q16
nOE
QFB
86962CYI-01
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REV. A DECEMBER 14, 2004
1
ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 12,
20, 28
Name
GND
Type
Description
Power supply ground.
Power
Input
Input
2
PCLK
nPCLK
Pulldown Non-inverting differential LVPECL clock input.
Pulldown/ Inverts differential LVPECL clock input.
Pullup
3
VDD/2 default when left floating.
4
5
F_RANGE
VDDA
Input
Pulldown PLL frequency range select. LVCMOS / LVTTL interface levels.
Analog supply pin.
Power
Output enable. Controls the enabling and disabling of outputs.
Pulldown When HIGH, forces Q0:Q16 to a HiZ state. When LOW,
enables clock outputs. LVCMOS / LVTTL interface levels.
6
nOE
Input
Feedback input to phase detector for generating clocks with
"zero delay". LVCMOS / LVTTL interface levels.
7
FB_IN
Input
Pulldown
8, 16, 24, 32
9
VDD
Power
Output
Power supply pins.
QFB
PLL feedback clock output. LVCMOS / LVTTL interface levels.
10, 11, 13,
14, 15, 17,
18, 19, 21,
Q16, Q15, Q14,
Q13, Q12, Q11,
Q10, Q9, Q8,
Output
Clock outputs. LVCMOS / LVTTL interface levels.
22, 23, 25, 26, Q7, Q6, Q5, Q4,
27, 29, 30, 31 Q3, Q2, Q1, Q0
NOTE: Pullup andPulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
KΩ
Pullup/Pulldown Resistors
51
KΩ
RVCC/2
CPD
VDD, VDDA = 3.465V
VDD, VDDA = 2.625V
VDD, VDDA = 3.465V
VDD, VDDA = 2.625V
7
pF
pF
Ω
Power Dissipation Capacitance
(per output)
8
14
18
ROUT
Output Impedance
Ω
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. CONTROL INPUT FUNCTION TABLE
Input/Output
Control Input
Control Input
Outputs
Q0:Q16
Enabled
HiZ
Frequency Range (MHz)
nOE
F_RANGE
Minimum
110
Maximum
140
0
1
0
1
60
110
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REV. A DECEMBER 14, 2004
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ICS86962I-01
Integrated
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Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
IDD
Power Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
120
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
QFB switching @100MHz with 50Ω to VDD/2
mA
mA
IDDA
15
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
IDD
Power Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
110
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
QFB switching @100MHz with 50Ω to VDD/2
mA
mA
IDDA
15
TABLE 4C. DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
V
DD = VIN = 3.465V,
IIN
Input Current
120
µA
VDD = VIN = 2.625V
VDD = VIN = 3.465V
VDD = VIN = 2.625V
2.6
1.8
V
V
VOH
VOL
Output High Voltage; NOTE 1
VDD = VIN = 3.465V,
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
0.5
V
VDD = VIN = 2.625V
VPP
PCLK, nPCLK
PCLK, nPCLK
0.15
1.3
VDD
V
V
Common Mode Input Voltage;
NOTE 2, 3
VCMR
GND + 1.2
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
86962CYI-01
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REV. A DECEMBER 14, 2004
3
ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
110
60
140
110
140
110
MHz
MHz
MHz
MHz
fREF
Input Frequency
110
60
fMAX
Output Frequency
Static Phase Offset; PCLK,nPCLK
NOTE 1 to FB_IN
t(Ø)
45
225
ps
tsk(o)
tjit(cc)
tjit(per)
tR, tF
Output Skew; NOTE 2, 3
Cycle-to-Cycle Jitter; NOTE 3
Period Jitter, RMS
210
100
4
ps
ps
ps
ns
ns
ns
ꢀ
Output Rise/Fall Time
20ꢀ to 80ꢀ
400
45
900
5
t
PLZ, tPHZ Output Disable Time
PZL, tPZH Output Enable Time
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
t
5
odc
f ≤ 133MHz
55
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_RANGE = 0
F_RANGE = 1
F_RANGE = 0
F_RANGE = 1
110
60
140
110
140
110
MHz
MHz
MHz
MHz
fREF
Input Frequency
110
60
fMAX
Output Frequency
Static Phase Offset; PCLK,nPCLK
NOTE 1 to FB_IN
t(Ø)
0
250
ps
tsk(o)
tjit(cc)
tjit(per)
tR, tF
Output Skew; NOTE 2, 3
Cycle-to-Cycle Jitter; NOTE 3
Period Jitter, RMS
175
80
3
ps
ps
ps
ns
ns
ns
ꢀ
Output Rise/Fall Time
20ꢀ to 80ꢀ
400
44
900
5
t
PLZ, tPHZ Output Disable Time
PZL, tPZH Output Enable Time
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
t
5
odc
f ≤ 133MHz
56
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
86962CYI-01
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REV. A DECEMBER 14, 2004
4
ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
,
VDD
,
VDDA
VDDA
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/ 3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
nPCLK
VPP
VCMR
Cross Points
Q0:Q16
PCLK
GND
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
DIFFERENTIAL INPUT LEVEL
nPCLK
PCLK
VOH
VOL
VOH
VREF
VOH
VREF
VOL
VOL
1σ contains 68.26ꢀ of all measurements
2σ contains 95.4ꢀ of all measurements
3σ contains 99.73ꢀ of all measurements
4σ contains 99.99366ꢀ of all measurements
6σ contains (100-1.973x10-7)ꢀ of all measurements
FB_IN
➤
t(Ø)
➤
Histogram
t(Ø) mean = Static Phase Offset
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET
PERIOD JITTER
86962CYI-01
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REV. A DECEMBER 14, 2004
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ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
VDD
2
80ꢀ
tF
80ꢀ
Qx
Qy
20ꢀ
20ꢀ
Clock
Outputs
VDD
tR
2
tsk(o)
OUTPUT RISE/FALL TIME
OUTPUT SKEW
VDD
2
Q0:Q16
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
86962CYI-01
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REV. A DECEMBER 14, 2004
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ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
A
PPLICATION NFORMATION
I
W
IRING THE
D
IFFERENTIAL
I
NPUT TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
P
OWER
SUPPLY
F
ILTERING
TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS86962I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
FIGURE 2. POWER SUPPLY FILTERING
86962CYI-01
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REV. A DECEMBER 14, 2004
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ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 3A to 3D show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
R1
120
R2
120
PCLK/nPCLK
FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
86962CYI-01
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REV. A DECEMBER 14, 2004
8
ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE for 32 Lead LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86962I-01 is: 1940
86962CYI-01
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REV. A DECEMBER 14, 2004
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ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
86962CYI-01
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REV. A DECEMBER 14, 2004
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ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
32 Lead LQFP
Count
Temperature
-40°C to 85°C
-40°C to 85°C
ICS86962CYI-01
ICS86962CYI-01T
ICS86962CYI01
ICS86962CYI01
250 per tray
1000
32 Lead LQFP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
86962CYI-01
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REV. A DECEMBER 14, 2004
11
ICS86962I-01
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVCMOS/LVTTL ZERO
DELAY
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
Page
3
Date
T4B
T8
2.5V Power Supply table - corrected the voltage from 3.3V to 2.5V.
Ordering Information Table - corrected Part/Order Number.
10/10/04
12/14/04
A
11
86962CYI-01
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REV. A DECEMBER 14, 2004
12
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