ICS87339AG-11T [IDT]
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | ICS87339AG-11T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87339-11 is a low skew, high perfor- • 2 divide by 2/4 differential 3.3V LVPECL outputs;
mance Differential-to-3.3V LVPECL / ECL Clock
Generator/Divider and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS87339-11 has one
2 divide by 4/5/6 differential 3.3V LVPECL outputs
HiPerClockS™
• 1 differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
differential clock input pair. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Input frequency: >1GHz (typical)
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS87339-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
• Output skew: 38ps (maximum)
• Part-to-part skew: 375ps (maximum)
• Bank skew: Bank A - TBD,
Bank B - TBD
• Propagation delay: 2.1ns (maximum)
• LVPECLmode operating voltage supply range:
VCC = 3V to 3.6V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3V to -3.6V
• -40°C to 85°C ambient operating temperature
• Compatible with MC10EP139, MC100EP139
BLOCK DIAGRAM
PIN ASSIGNMENT
DIV_SELA
VCC
nCLK_EN
DIV_SELB0
CLK
VCC
1
2
3
4
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
VEE
D
nCLK_EN
÷2, ÷4
QA1
nQA1
Q
R
nCLK
nc
MR
5
6
7
8
9
10
LE
CLK
nCLK
VCC
DIV_SELB1
DIV_SELA
QB0
nQB0
ICS87339-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
÷4, ÷5, ÷6
QB1
nQB1
R
MR
DIV_SELB0
DIV_SELB1
Top View
20-Lead SOIC
7.5mm x 12.8mm x 2.25mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87339AG-11
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REV. A MAY 15, 2003
1
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 8, 20
2
Name
VCC
Type
Description
Power
Input
Positive supply pins.
nCLK_EN
Pulldown Clock enable. LVCMOS / LVTTL interface levels.
Selects divide value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
3
DIV_SELB0
Input
Pulldown
4
5
6
CLK
nCLK
nc
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
No connect.
Unused
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go
high. When logic LOW, the internal dividers are the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
7
MR
Input
Input
Pulldown
9
DIV_SELB1
Pulldown
Pulldown
Selects divide value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
10
DIV_SELA
VEE
Input
11
Power
Negative supply pin.
12, 13
14, 15
16, 17
18, 19
nQB1, QB1 Output
nQB0, QB0 Output
nQA1, QA1 Output
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
MR nCLK_EN
DIV_SELA
DIV_SELB0
DIV_SELB1 QA0, QA1 nQA0, nQA1 QB0, QB1 nQB0, nQB1
1
0
X
1
X
X
X
X
LOW
HIGH
LOW
HIGH
Not
Switching
Not
Switching
Not
Switching
Not
Switching
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷2
÷2
÷2
÷2
÷4
÷4
÷4
÷4
÷2
÷2
÷2
÷2
÷4
÷4
÷4
÷4
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
÷4
÷5
÷6
÷5
NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.
87339AG-11
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REV. A MAY 15, 2003
2
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
3.6
V
85
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
nCLK_EN, MR,
DIV_SELA, DIV_SELBx
nCLK_EN, MR,
IIH
IIL
VIN = VCC = 3.6V
150
µA
µA
Input Low Current
VIN = 0V, VCC = 3.6V
-5
DIV_SELA, DIV_SELBx
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.6V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
VIN = VCC = 3.6V
150
nCLK
CLK
VIN = 0V, VCC = 3.6V
VIN = 0V, VCC = 3.6V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
87339AG-11
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REV. A MAY 15, 2003
3
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical
VCC - 1.4
Maximum Units
VOH
Output High Voltage; NOTE1
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VSWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Input Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
>1
GHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
CLK to Q (Diff)
1.65
2.1
38
tsk(o)
ps
Bank A
Bank B
TBD
TBD
ps
tsk(b)
Bank Skew; NOTE 3, 5
ps
tsk(pp)
tR / tF
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
375
600
ps
20% to 80%
200
ps
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points
NOTE 3: Defined as skew within a bank of outputs and with equal load conditions.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
87339AG-11
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REV. A MAY 15, 2003
4
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V
VCC
SCOPE
Qx
nCLK
VPP
VCMR
LVPECL
Cross Points
CLK
VEE
nQx
VEE = -1.3V ± 0.3V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
CLK
80%
80%
VSWING
20%
20%
nQAx,
nQBx
Clock Outputs
t
t
F
R
QAx,
QBx
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
87339AG-11
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REV. A MAY 15, 2003
5
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
50Ω transmission lines. Matched impedance techniques should
tion for LVPECL outputs. The two different layouts mentioned be used to maximize operating frequency and minimize signal
are recommended only as guidelines.
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
87339AG-11
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REV. A MAY 15, 2003
6
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. Both VSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTLdrivers. If you are using an LVHSTLdriver
the most common driver types. The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
87339AG-11
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REV. A MAY 15, 2003
7
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87339-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87339-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 85mA = 306mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.6V, with all outputs switching) = 306mW + 120.8mW = 426.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6Abelow.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.427W * 66.6°C/W = 113.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6A. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
q
by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance qJA for 20-pin SOIC, Forced Convection
q
by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
87339AG-11
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REV. A MAY 15, 2003
8
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
87339AG-11
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REV. A MAY 15, 2003
9
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TSSOP TABLE
q
by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW SOIC TABLE
q
by Velocity (Linear Feet per Minute)
0
JA
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87339-11 is: 1745
87339AG-11
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REV. A MAY 15, 2003
10
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
87339AG-11
www.icst.com/products/hiperclocks.html
REV. A MAY 15, 2003
11
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
PACKAGE OUTLINE - M SUFFIX
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
87339AG-11
www.icst.com/products/hiperclocks.html
REV. A MAY 15, 2003
12
PRELIMINARY
ICS87339-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW,
÷2/4,÷4/5/6,
DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS87339AG-11
ICS87339AG-11T
ICS87339AM-11
ICS87339AM-11T
Marking
Package
20 lead TSSOP
Count
72 per Tube -40°C to 85°C
2500 -40°C to 85°C
38 per Tube -40°C to 85°C
1000 -40°C to 85°C
Temperature
ICS87339AG11
ICS87339AG11
ICS87339AM11
ICS87339AM11
20 lead TSSOP on Tape and Reel
20 lead SOIC
20 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
87339AG-11
www.icst.com/products/hiperclocks.html
REV. A MAY 15, 2003
13
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