ICS9147-01 [IDT]
Frequency Generator & Integrated Buffers for PENTIUMTM; 频率发生器和集成缓冲器对PENTIUMTM
| 型号： | ICS9147-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUMTM |
| 文件： | 总11页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9147-01
Systems, Inc.
Frequency Generator & Integrated Buffers for PENTIUMTM
General Description
Features
•
•
•
Four copies of CPU clock
Six SDRAM (3.3V TTL), usable as AGP clocks
Seven copies of BUS clock (synchronous with CPU
clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU)
The ICS9147-01 generates all clocks required for high
speed RISC or CISC microprocessor systems such as Intel
PentiumPro. Two bidirectional I/O pins (FS1,FS2) are latched
at power-on to the functionality table, with FS0 selectable
in real-time to toggle between conditions. The inputs
provide for tristate and test mode conditions to aid in
system level testing. These multiplying factors can be
customized for specific applications. Glitch-free stop
clockcontrols are provided for CPU clocks and BUS clocks.
•
•
•
•
•
CPU clocks to BUS clocks skew 1-4ns (CPU early)
One IOAPIC clock @14.31818 MHz
Two copies of Ref. clock @14.31818 MHz
One each 48/24 MHz (3.3 V TTL)
This device is configured into the Mobile mode for
power management of Intel 430 TX
High drive BUS and SDRAM outputs typically provide
greater than 1V/ns slew rate into 30pF loads. CPU outputs
typically provide better than 1V/ns slew rate into 20pF
•
•
•
Ref. 14.31818 MHz Xtal oscillator input
Separate 66/60 MHz select pin (LSB of select pins)
Separate VDD2 for four CPU and single IOAPIC output
buffers to allow 2.5V output (or Std. Vdd)
50 ±
loads while maintaining
5% duty cycle. The REF clock
outputs typically provide better than 0.5V/ns slew rates.
Seperate buffers supply pins VDD2 allow for 3.3V or
reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and
IOAPIC outputs.
•
•
•
Power Management Control Input pins
3.0V – 3.7V supply range w/2.5V compatible outputs
48-pin SSOP package
Block Diagram
Pin Configuration
48-Pin SSOP
Pentium is a trademark of Intel Corporation
9147-01RevB04/25/01
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9147-01
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
REF2
OUT Reference clock output*
1
FS2
IN
Logic input frequency select Bit 2*
REF1
FS1
OUT Reference clock output*
2
IN
Logic input frequency select Bit1*
3, 10, 17, 24, 31,
37, 43
GND
PWR Ground.
Crystal input. Nominally 14.318 MHz. Has internal load cap. External
crystal load of 30pF to GND recommended for VDD power on faster
than 2.0ms.
4
X1
IN
Crystal output. Has internal load cap and feedback resistor to X1.
5
X2
OUT External crystal load of 10pF to GND recommended for VDD power
on faster than 2.0ms.
7, 15, 28, 34
8,9,11,12,13,14,16 BUSF, BUS(1:6)
VDD3
PWR 3.3V I/O power supply, BUS and SDRAM buffer supply.
OUT BUS clock outputs. see select table for frequency
Select pin for enabling 66.6 MHz or 60 MHz, or other selections in
18
FSO
IN
frequency select table.
21, 25, 48
22, 23
VDD
48, 24MHz
PWR Core power supply, and fixed clock power.
OUT 48, 24MHz clock outputs
Input pin to synchronously stop all BUS (1:6) clocks when pin is
26
BUSSTOP#
CPUSTOP#
SDRAM (1:6)
IN
low.
Input pin to synchronously stop all CPU and SDRAM clocks when
27
IN
pin is low.
36, 35, 33, 32, 30,
29
SDRAM clocks at CPU speed. See select table for frequency.
OUT
Powered by VDD3.
2.5V Power Supply for CPU and IOAPIC buffers, can be tied to
40, 46
41, 42, 39,38
44
VDD2
CPU (1:4)
PD#
PWR
VDD3 for 3.3V operation
OUT CPU clock output clocks .See select table for frequency
Power down logic control input. When low, powers off both PLL
IN
and all outputs forced to logic low.
IOAPIC clock output (Freq=14.318 with nominal crystal) Powered
45
IOAPIC
N/C
OUT
by VDD2 supply
6, 19, 20, 47
—
Pins not internally connected.
* Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic
Hi to VDD or GND for logic low.
2
ICS9147-01
Functionality
CPU (1:4),
SDRM
(1:6)
BUS (1:6)
BUSF
REF (1:2),
CPU-
PD#
BUS-
FS2*
FS1*
FS0
48MHz 24 MHz
(MHz) (MHz)
IOAPIC
STOP# STOP# (at REF2) (at REF1) (pin 18)
(MHz)
(MHz)
(MHz)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
60
66.6
50
55
75
30
33.3
25
48
48
24
24
14.318
14.318
14.318
14.318
14.318
14.318
REF
48
24
27.5
48
24
30a
48
24
83.3
REF/2
Tristate
33.3a
REF/4
Tristate
48
24
REF/2
REF/4
Tristate Tristate
Tristate
LOW
LOW
LOW
0
1
1
X
X
X
LOW
LOW
PLL off
PLL off
Osc Off
1
1
0
1
1
0
X
X
X
X
X
X
LOW
running
running
LOW
running
running
running
running
running
running
Note a: These frequency selections are at CPU/2.5 (internal VCO/5), not synchronous CPU/2
3
ICS9147-01
CPUSTOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPUSTOP# is synchronized by the ICS9147-01. All other clocks will continue to run while the CPU and SDRAM clocks
are disabled. The CPU and SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse. CPU clock on latency is 0 to 1 CPU clocks and CPU clock off latency is 0 to 1 CPU
clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPUSTOP# is an asynchronous input and metastable conditions
may exist. This signal is synchronized to the CPU and SDRAM
clocks inside the ICS9147-01.
3. All other clocks continue to run undisturbed.
4. PD# and BUSSTOP# are shown in a high (true) state.
BUSSTOP#Timing Diagram
BUSSTOP# is an asynchronous input to the ICS9147-01. It is used to turn off the BUS (1:6) clocks for low power operation.
BUSSTOP# is synchronized by the ICS9147-01 internally. BUS (1:6) clocks are stopped in a low state and started with
a full high pulse width guaranteed. BUS (1:6) clock on latency cycles are less than 4 CPU clocks and BUS (1:6) clock off
latency is less than 4 clocks.
(Drawing shown on next page.)
4
ICS9147-01
Notes:
1. All timing is referenced to the Internal BUS clock (defined as inside the ICS9147 device.)
2. BUSSTOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be
synchronized inside the ICS9147.
3. All other clocks continue to run undisturbed.
4. PD# and CPUSTOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal is synchronized internal by the ICS9147-01 prior to its control
action of powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal
clocks will not be running after the device is put in power down state. When PD# is active (low) all clocks are driven to
a low state and held prior to turning off the VCOs and the Crystal oscillator. The power on latency is guaranteed to be
less than 3mS. The power down latency is less than three CPU clock cycles. BUSSTOP# and CPUSTOP# are don’t care
signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPU clock (defined as inside the ICS9147 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9147.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
5
ICS9147-01
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 – 70°C unless otherwise stated
DC Characteristics
TEST CONDITIONS
Latched inputs and Fulltime inputs
Latched inputs and Fulltime inputs
VIN = 0V (Fulltime inputs)
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
SYMBOL
VIL
MIN
-
TYP
-
-
-10.5
-
30.0
30.0
-26.0
-12.5
25.0
-22.0
33.0
33.0
-45.0
-13.0
0.3
0.3
2.8
2.1
0.3
2.8
0.3
0.3
2.8
MAX
0.2VDD
-
-
5.0
-
UNITS
V
V
VIH
IIL
IIH
IOL1a
IOL1b
IOH1a
IOH1b
IOL2
0.7VDD
-28.0
-5.0
19.0
19.0
-
A
A
VIN=VDD (Fulltime inputs)
VOL = 0.8V; CPU, SDRAM; VDD2 = 3.3V
VOL = 0.8V; CPU; VDD2 = 2.5V
VOH = 2.0V; CPU, SDRAM; VDD2 = 3.3V
VOH = 2.0V; CPU; VDD2 = 2.5V
VOL = 0.8V; for fixed 24, 48, BUS, REF
VOH = 2.0V; for fixed 24, 48, BUS, REF
VOL = 0.8V; IOAPIC; VDD2 = 3.3V
VOL = 0.8V; IOAPIC; VDD2 = 2.5V
VOH = 2.0V for IOAPIC at VDD2 = 3.3V
VOH = 2.0V; IOAPIC; VDD2 = 2.5V
IOL = 10mA; CPU, SDRAM;VDD2 = 3.3V
IOL = 10mA; CPU; VDD2=2.5V
IOH = -10mA; CPU, SDRAM; VDD = 3.3V
IOH = -10mA; CPU; VDD2=2.5V
IOL = 8mA; for fixed CLKs
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
V
Output Low Current
-16.0
-9.5
-
-14.0
-
Output High Current
Output Low Current
Output High Current
16.0
-
19.0
19.0
-
IOH2
IOL3a
IOL3b
IOH3a
IOH3b
VOL1a
VOL1b
VOH1a
VOH1b
VOL2
VOH2
VOL3a
VOL3b
VOH3a
VOH3b
IDD
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
-16.0
-10.0
0.4
0.4
-
-
2.4
1.95
-
2.4
-
Output Low Voltage
Output High Voltage
0.4
-
0.4
0.4
-
IOH = -8mA; for fixed CLKs
IOL = 10mA; for IOAPIC at VDD2 = 3.3V
IOL = 10mA; IOAPIC; VDD2 = 2.5V
IOH = -10mA; for IOAPIC at VDD2 = 3.3V
IOH = -10mA; IOAPIC; VDD2 = 2.5V
@66.6 MHz; all outputs unloaded
Output Low Voltage
2.4
2.0
-
Output High Voltage
2.2
120
300
-
V
mA
A
Supply Current
Supply Current
180
500
IDDPD
Power Down
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS9147-01
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7 V, TA = 0 – 70°C unless otherwise stated
AC Characteristics
TEST CONDITIONS
PARAMETER
Rise Time1
SYMBOL
Tr1a
MIN
-
TYP
0.9
MAX
1.5
UNITS
ns
20pF load, 0.8 to 2.0V
CPU; VDD = 3.3V
20pF load, 0.8 to 2.0V
Rise Time1
Tr1b
-
1.5
2.0
ns
CPU; VDDL @ 2.5V
Fall Time1,3
Rise Time1
Fall Time1
Rise Time1
Fall Time1
Rise Time1,3
Rise Time1
Fall Time1,3
Rise Time1
Fall Time1
Tf1
Tr2
Tf2
Tr3
Tf3
20pF load, 2.0 to 0.8V CPU;
30pF load SDRAM 0.8 to 2.0V
30pF load SDRAM 2.0 to 0.8V
30pF load BUS 0.8 to 2.0V
30pF load BUS 2.0 to 0.8V
20pF load, 0.8 to 2.0V
-
-
-
-
-
0.8
1.0
0.9
1.2
1.1
1.4
1.6
1.5
2.0
1.9
ns
ns
ns
ns
ns
Tr4
Tr4a
Tf4
-
-
-
0.83
1.4
2.6
1.3
2.0
2.0
ns
ns
ns
ns
ns
24, 48, REF2, & IOAPIC
45pF load, 0.8 to 2.0V , IOAPIC with
VDDL = 2.5V
2.2
20pF load, 2.0 to 0.8V
0.81
1.6
24, 48, REF2, & IOAPIC
Load = 45pF 0.8 to 2.0V IOAPIC
VDD = 3.3V
Tr5
Load = 45pF 2.0 to 0.8V, REF1
VDD = 3.3V
Tf5
1.6
Duty Cycle1
Dt
Tjc-c
20pF load @ VOUT=1.4V
CPU, VDD2 = 3.0 to 3.7V
CPU; Load=20pF,
45
50
150
55
250
%
ps
Jitter, Cycle to Cycle1
Jitter, One Sigma1, 2
Jitter, Absolute1, 2
Jitter, One Sigma1
Jitter, Absolute1
Tj1s1
Tjab1
Tj1s2
Tjab2
-
-250
-
50
150
250
3
ps
ps
%
%
SDRAM & BUS Clocks Load = 30pF
CPU; Load=20pF,
-
SDRAM & BUS Clocks Load = 30p
REF2, 48/24MHz Load=20pF,
REF1 CL = 47pF
1
REF2, 48/24MHz Load=20pF,
REF1 CL = 47pF
-5
2
5
Input Frequency1
Fi
12.0
-
-
14.318
16.0
-
-
MHz
pF
pF
Logic Input Capacitance1
CIN
Logic input pins
X1, X2 pins
From VDD=1.6V to 1st crossing of 66.6
MHz VDD supply ramp < 40ms
CPU to CPU; Load=20pF; @1.4V
(Same VDD)
BUS to BUS; Load=20pF; @1.4V
CPU to BUS; Load=20pF; @1.4V
(CPU is early)
SDRAM (@3.3V) to CPU (@2.5V)
(2.5V CPU is late)
5
Crystal Oscillator Capacitance1
CINX
18
Power-on Time1
ton
-
2.5
4.5
ms
Clock Skew1
Clock Skew1
Clock Skew1,2
Tsk1
Tsk2
Tsk3
-
150
300
2.6
250
500
4
ps
ps
ns
-
1
Clock Skew1
Tsk4
250
400
ps
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Note 2: Includes VDD2 = 2.5V
Note 3: VDD3 = 3.3V
7
ICS9147-01
Shared Pin Operation -
Input/Output Pins
Test Mode Operation
The ICS9147-01 includes a production test verification
mode of operation. This requires that the FSO and FS1 pins
be programmed to a logic high and the FS2 pin be
programmed to a logic low(see Shared Pin Operation
section). In this mode the device will output the following
frequencies.
Pins 1 and 2 on the ICS9147-01 serve as dual signal functions
to the device. During initial power-up, they act as input
pins. The logic level (voltage) that is present on these pins at
this time is read and stored into a 4-bit internal data latch. At
the end of Power-On reset, (seeAC characteristics for timing
values), the device changes the mode of operations for these
pins to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
Pin
Frequency
REF, IOAPIC REF
48MHz
24MHz
CPU,
REF/2
REF/4
REF/2
REF/4
To program (load) the internal configuration register for
these pins, a resistor is connected to either theVDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
SDRAM
BUS (1:6)
Note: REF is the frequency of either the crystal connected
between the devices X1and X2 or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor
loading option where either solder spot tabs or a physical
jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Fig. 1
8
ICS9147-01
Fig. 2a
Fig. 2b
9
ICS9147-01
Recommended PCB Layout for ICS9147-01
NOTE:
This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of
components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible
to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced
with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the
different Vdd planes.
10
ICS9147-01
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
α
A1
- CC --
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
15.75
MAX
16.00
MIN
.620
MAX
.10 (.004)
C
48
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9147F-01
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
11
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