ICS9169CM-23 [IDT]
Processor Specific Clock Generator, 83.3MHz, PDSO28, 0.300 INCH, SOIC-28;
| 型号： | ICS9169CM-23 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 83.3MHz, PDSO28, 0.300 INCH, SOIC-28 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS9169C-23
FrequencyGeneratorforPentium™BasedSystems
General Description
Features
•
•
•
•
Eight selectable CPU clocks operate up to 83.3 MHz
Maximum CPU jitter of ±200ps
Six BUS clocks support sync or async bus operation
250ps skew window for CPU outputs, 500ps skew window
for BUS outputs
CPU clocks to BUS clocks skew 1-4 ns (CPU early)
48 MHz clock for USB support & 24 MHz clock for FD.
Logic inputs latched at Power-On for frequency selection
saving pins as Input/Output
Integrated buffer outputs drive up to 30pF loads
The ICS9169C-23 is a low-cost frequency generator designed
specifically for Pentium-based chip set systems. The
integrated buffer minimizes skew and provides all the clocks
required. A 14.318 MHz crystal provides the reference
clock to generate standard Pentium frequencies. The CPU
clock makes gradual frequency transitions without
violating the PLL timing of internal microprocessor clock
multipliers.
•
•
•
Either synchronous (CPU/2) or asynchronous (32 MHz) PCI
bus operation can be selected by latching data on BSEL
input.
•
•
3.0V - 3.7V supply range, CPU (1:6) outputs 2.5V
(2.375 - 2.6V) VDD option
•
28-pin SOIC package
Pin Configuration
Block Diagram
28-Pin SOIC
Functionality
3.3V±10%, 0-70°C
Crystal (X1, X2) = 14.31818 MHz
ADDRESS
SELECT
FS2 FS1 FS0
CPU(1:8) BUS (1:6)MHz
(MHz)
48MHz 24MHz REF
BSEL=1 BSEL=0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
60
25
30
32
32
32
48
48
48
24
24
REF
REF
REF
REF
REF
REF
REF
VDD Groups:
Latched Inputs:
L1 = BSEL
L2 = FS0
VDD1 = X1, X2, REF/BSEL
VDD2 = CPU1-6
66ꢀ6
REF/2
55
33ꢀ3
24
REF/4 REF/3 REF/2
REF/4
24
VDD3 = CPU7-8 & PLL Core
VDD4 = BUS1-6
VDD5 = 48/24 MHz
L3 = FS1
L4 = FS2
27ꢀ5
37ꢀ5
41ꢀ7
32
32
32
48
48
48
75
24
83ꢀ3
24
Tristate Tristate Tristate Tristate Tristate Tristate
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
9169-23RevC01/09/02
ICS9169C-23
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
X1
PWR
Power for control logicꢀ
XTAL or external reference frequency inputꢀ This input includes XTAL load
capacitance and feedback bias for a 12-16MHz crystal, nominally
14ꢀ31818MHzꢀ External crystal load of 30pF to GND recommended for VDD
power on faster than 2ꢀ0msꢀ
2
IN
XTAL output drive from deviceꢀ External crystal load of 10pF to GND
recommended for VDD power on faster than 2ꢀ0msꢀ
3
X2
OUT
PWR
OUT
4,11,16,22
6,7,9,10,15
GND
Ground for control logicꢀ
Processor clock outputs which are a multiple of the input reference clock as
shown in the preceding tableꢀ
CPU(2:5),8
Power for CPU 1-6 clock buffers onlyꢀ This VDD supply can be reduced to
2ꢀ5V for CPU (1:6) outputsꢀ
8
VDD2
PWR
24, 23, 21,
20, 18, 17
BUS clock outputs which are a multiple of the input reference clock as shown in
the preceding tableꢀ
BUS(1:6)
VDD4
OUT
PWR
OUT
19
Power for BUS# fixed mode deviceꢀ
Fixed 24 MHz clock (assuming a 14ꢀ31818 MHz
REF frequency)ꢀ
26
24 MHz
Fixed 48 MHz clock (assuming a 14ꢀ31818 MHz
REF frequency)ꢀ
27
28
48 MHz
REF
OUT
OUT
Fixed 14ꢀ31818 MHz clock (assuming a 14ꢀ31818 MHz
REF frequency)ꢀ
Selection for synchronous (High) or asynchronous (Low) bus clock operationꢀ
See shared pin programming description later in this data sheet for further
explanationꢀ
BSEL
IN
Processor clock outputs which are a multiple of the input reference clock as
shown in the preceding tableꢀ
CPU 1
FS0
OUT
IN
5
Frequency multiplier select pinsꢀ See shared pin programming description later in
this data sheet for further explanationꢀ*
Processor clock outputs which are a multiple of the input reference clock as
shown in the preceding tableꢀ
CPU (6:7)
FS (1:2)
OUT
IN
12,13
Frequency multiplier select pinsꢀ See shared pin programming description later in
this data sheet for further explanationꢀ*
Power for CPU7-8 clock buffers and internal PLL and Core logicꢀ Must be
nominal 3ꢀ3V (3ꢀ0 to 3ꢀ7V)
14
25
VDD3
VDD5
PWR
PWR
Power for 24/48 MHz output bufferꢀ
* The internal pull-up will vary from 350K to 500K based on temperature.
2
ICS9169C-23
Shared Pin Operation -
Input/Output Pins
Test Mode Operation
The ICS9169C-23 includes a production test verification
mode of operation. This requires that the FSO and FS1 pins
be programmed to a logic high and the FS2 pin be
programmedtoa logiclow(see SharedPinOperationsection).
In this mode the device will output the following
frequencies.
Shared Pin Operation - Input/Output, Pins 5, 28, 12 and
13 on the ICS9169C-23 serve as dual signal functions to
the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at this
time is read and stored into a 4-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for these
pins to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
Pin
Frequency
REF
REF/2
REF/4
REF2
REF/4
REF/3
REF
48MHz
24MHz
CPU (1:8)
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
BSEL=1
BESEL = 0
BUS (1:6)
Note: REF is the frequency of either the crystal connected
between the devices X1and X2 or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor
loading option where either solder spot tabs or a physical
jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Fig. 1
3
ICS9169C-23
Fig. 2b
Fig. 2a
Fig. 3
4
ICS9169C-23
Technical Pin Function Descriptions
VDD
clocks is controlled by the supply that is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
This is the power supply to the internal logic of the device
as well as the following clock output buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. Fixed clock output buffers
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
CPUL, BUS, SDRAM, AGP and IOAPIC pins. See the Fun-
tionality table at the beginning of this data sheet for a list
of the specific frequencies that this clock operates at and
the selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up and
stores the programmed selection code in an internal data
latch. (See programming section of this data sheet for
configuration circuitry recommendations.
This pin may be operated at any voltage between 3.0 and
5.5 volts. Clocks from the listed buffers that it supplies
will have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
GND
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output
buffers:
BSEL
When this pin is a logic 1, it will place the CPU clocks in
the synchronous mode (running at half the frequency of
the Ref). If this pin is a logic 0, it will be in the asynchronous
mode for the CPU clocks and will operate at the
preprogrammed fixed frequency rate. It is a shared pin
and is programed the same way as the Frequency Select
pins.
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal.
When the device is driven by an external clock signal, X1
is the device’ input pin for that reference clock. This pin
also implements an internal crystal loading capacitor that
is connected to ground. See the data tables for the value of
the capacitor.
VDD 2, 3
These are the power supply pins for the CPU clock buffers.
By separating the clock power pins, each group can receive
the appropriate power decoupling and bypassing necessary
to minimize EMI and crosstalk between the individual
signals. VDD2 can be reduced to 2.5V VDD for advanced
processor clocks, which will bring CPU (1:6) outputs at 0
to 2.5V output swings.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2
is an output signal that drives (or excites) the discrete
crystal. This pin also implements an internal crystal loading
capacitor that is connected to ground. See the data tables
for the value of the capacitor.
48 MHz
This is a fixed frequency clock that is typically used to
drive Super I/O peripheral device needs.
24 MHz
This is a fixed frequency clock that is typically used to
drive Keyboard controller clock needs.
CPU (1:8)
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of
these clocks is controlled by that which is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies this clock operates at and the selection codes
that are necessary to produce these frequencies.
VDD4
This power pin supplies the BUS clock buffers.
REF
This is a fixed frequency clock that runs at the same
frequency as the input reference clock (typically 14.31818
MHz) is and typically used to drive Video and ISA BUS
requirements.
BUS (1:6)
VDD5
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
This power pin supplies the 48/24 MHz clocks.
5
ICS9169C-23
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
DC Characteristics
TEST CONDITIONS
PARAMETER
SYMBOL
VIL
MIN
-
TYP
MAX
UNITS
V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
-
0ꢀ2VDD
VIH
IIL
0ꢀ7VDD
-28ꢀ0
-5ꢀ0
-
-10ꢀ5
-
-
-
V
VIN=0V
VIN=VDD
µA
IIH
5ꢀ0
µA
IOL
VOL=0ꢀ8V; for CPU, BUS,
Fixed CLKs
Output Low Current1
Output High Current1
16ꢀ0
-
25ꢀ0
-
mA
mA
IOH
VOL=2ꢀ0V; for CPU, BUS,
Fixed CLKs
-30ꢀ0
-14ꢀ0
Output Low Current1
Output High Current1
VOL=0ꢀ8V; for Ref CLK
VOL=2ꢀ0V; for Ref CLK
19ꢀ0
-
30ꢀ0
-
mA
mA
IOL
IOH
-38ꢀ0
-16ꢀ0
VOL
IOL=8mA; for CPU, BUS,
Fixed CLKs
Output Low Voltage1
Output High Voltage1
-
0ꢀ3
2ꢀ8
0ꢀ4
-
V
V
VOH
IOH=-8mA; for CPU, BUS,
Fixed CLKs
2ꢀ4
Output Low Voltage1
Output High Voltage1
Supply Current
IOL=10mA; for Ref CLK
-
2ꢀ4
-
0ꢀ3
2ꢀ8
70
0ꢀ4
-
V
V
VOL
VOH
IDD
IOH=-15mA; for Ref CLK
@66ꢀ6 MHz; all outputs unloaded
140
mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS9169C-23
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.7V, TA = 0 –70°C unless otherwise stated
AC Characteristics
SYMBOL TEST CONDITIONS
PARAMETER
Rise Time1
MIN
TYP
0ꢀ9
0ꢀ8
1ꢀ5
1ꢀ4
50
MAX
1ꢀ5
UNITS
ns
20pF load, 0ꢀ8 to 2ꢀ0V
CPU & BUS
Tr1
Tf1
-
-
Fall Time1
20pF load, 2ꢀ0 to 0ꢀ8V CPU & BUS
20pF load, 20% to 80% CPU & BUS
20pF load, 80% to 20%CPU & BUS
20pF load @ VOUT=1ꢀ4V
1ꢀ4
ns
Rise Time1
Tr2
Tf2
-
2ꢀ5
ns
Fall Time1
-
2ꢀ4
ns
Duty Cycle1
Jitter, One Sigma1
Dt
45
-
60
%
CPU & BUS Clocks; Load=20pF,
BSEL=1
Tj1s1
50
150
ps
CPU & BUS Clocks; Load=20pF,
BSEL=1
Jitter, Absolute1
Tjab1
Tj1s2
Tjab2
Fi
-250
-
250
ps
%
Jitter, One Sigma1
Ref & Fixed CLKs; Load=20pF
Ref & Fixed CLKs; Load=20pF
-
1
2
3
5
Jitter, Absolute1
-5
%
Input Frequency1
12ꢀ0
14ꢀ318
5
16ꢀ0
-
MHz
pF
Logic Input Capacitance1
Crystal Oscillator Capacitance1
Power-on Time1
CIN
CINX
ton
Logic input pins
X1, X2 pins
-
-
-
18
-
pF
From VDD=1ꢀ6V to 1st crossing of 66ꢀ6
MHz VDD supply ramp < 40ms
From 1st crossing of acquisition to
< 1% settling
2ꢀ5
4ꢀ5
ms
Frequency Settling Time1
Clock Skew1
ts
-
-
2ꢀ0
150
160
2ꢀ2
4ꢀ0
250
500
4
ms
ps
ps
ns
Tsk1
Tsk2
Tsk3
CPU to CPU; Load=20pF; @1ꢀ4V
BUS to BUS; Load=20pF; @1ꢀ4V
Clock Skew1
-
CPU to BUS; Load=20pF; @1ꢀ4V
(CPU is early)
Clock Skew1
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS9169C-23
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.10
2.05
0.33
0.18
MAX
2.65
--
2.55
0.51
0.32
MIN
--
.0040
.081
.013
.007
SEE VARIATIONS
.291 .299
0.050 BASIC
MAX
.104
--
.100
.020
.013
A
A1
A2
B
C
D
E
SEE VARIATIONS
7.40
7.60
e
1.27 BASIC
H
h
L
10.00
0.25
0.40
10.65
0.75
1.27
.394
.010
.016
.419
.029
.050
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
MAX
.724
N
MIN
17.70
MAX
18.40
MIN
.697
28
Reference Doc.: JEDEC Publication 95, MS-013 & MO-119
300 mil (Wide Body) SOIC
10-0031
Ordering Information
ICS9169CM-23
Example:
ICS XXXX F- PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
PackageType
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
8
相关型号：
ICS9169CM-23LF
Processor Specific Clock Generator, 83.3MHz, PDSO28, 0.300 INCH, ROHS COMPLIANT, MS-013, MO-119, SOIC-28
IDT
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